Abstract: A configurable synchronizer (10) for DDR-SDRAM (12) is provided that includes a strobe select module (40) operable to receive a memory select signal (106) and to pass strobe signals (20, 30) from one or more DDR-SDRAMs (16, 18) to a number of synchronizer circuits (44) corresponding to data signals (17) passed in parallel by each DDR-SDRAM as indicated by the memory select signal (106). A rising edge latch (174) receives a rising edge data signal (170) and latches the rising edge data signal (170) through the rising edge latch (174) on a rising edge of the strobe signal (152). A falling edge latch (176) receives a falling edge data signal (172) and latches the falling edge data signal (172) through the falling edge latch (176) on a falling edge of the strobe signal (152).

Abstract: A bipolar ECL latch or flip-flop circuit of the isolated differential feedback type provides a high level of alpha particle immunity, without unduly affecting the propagation delay, power dissipation or circuit area in an integrated circuit device. A pair of latch transistors having differential input are used, with common emitters coupled to a clocked current source. The latch outputs are coupled back to a pair of holding transistors by two emitter follower feedback transistors. The holding transistors have a common emitter connection to a current source clocked inversely to that of the current source for the latch transistors, so the state of the latch is held by the holding transistors. The amplification of the feedback transistors is reduced so that the speed with which the transistor can react to transient noise such as that produced by an alpha hit is reduced.

Abstract: An alpha particle resistant memory cell and array with complementary, differential data in, data out and write enable inputs capable of independent, simultaneous read/write operations. During write operations, clocked differential write and data inputs steer cell current to induce differential cell voltages indicative of the stored data. During read operations, a read select input shifts the voltage levels of the selected cell to produce a distinguishable output which dominates over the other cells to appropriately steer current at a sense amplifier to identify the binary cell contents. A 64 row by 12 bit register stack, with split word write, master reset and read enable is also disclosed.

Abstract: A vacuum shield support ring for a high voltage vacuum interrupter contains a plurality of quasi rectangular openings equidistantly spaced around the ring to allow for the upward flow of glass during the vacuum interrupter envelope forming process. Complete embedment of the openings substantially reduces the occurrence of ionized particles in the finished vacuum interrupter.