Abstract: According to one embodiment, a controller for a surveillance system includes ports for coupling a camera, synchronization logic blocks coupled to the ports, an information aggregation logic block coupled to the camera ports, and an output port coupled to the information aggregation logic block. According to another embodiment, a method of scaling a surveillance system includes synchronizing a plurality of cameras, capturing images from the synchronized cameras, aggregating at least two processed synchronized images, and processing the aggregated synchronized images.

Abstract: A method of partitioning an algorithm between hardware and software includes accepting a user defined algorithm specified in a source code, identifying worker methods and feature extraction methods within the user defined algorithm, replacing worker methods in the source code with hardware logic, replacing feature extraction methods with a combination of hardware logic and software libraries that interface with the hardware logic, and outputting an FPGA programming specification of the hardware logic and interface libraries.

Abstract: A method and system for tracking a subject through an environment that includes collecting visual data representing a physical environment from a plurality of cameras; processing the visual data; constructing a model of the environment from the visual data; and cooperatively tracking a subject in the environment with the constructed model and processed visual data.

Abstract: An automated system and method for programming field programmable gate arrays (FPGAS) is disclosed for implementing user-defined algorithms specified in a high level language. The system is particularly suited for use with image processing algorithms and can speed up the process of implementing and testing a fully written high-level user-defined algorithm to a matter of a few minutes, rather than the days, weeks or even months presently required using conventional software tools. The automated system includes an analyzer module and a mapper module. The analyzer determines what logic components are required and their interrelationships, and observes the relative timing between the required components and their partial products. The mapper module utilizes the output from the analyzer module and determines where the required logic components must be placed on a given target FPGA in order to reliably route, without interference, the required interconnections between various components and I/O.

Abstract: The sensor system of the preferred embodiment includes a sensor, a sensor configuration ROM adapted to store a sensor description including a root directory, a unit directory, a first dependent unit directory to configure the sensor as a first virtual sensor device, a second dependent unit directory to configure the sensor as a second virtual sensor device, and a software driver adapted to interface with the first virtual sensor device and the second virtual sensor device. The sensor system of the preferred embodiments extends the conventional IIDC camera software model to include the concept of multiple sensor/camera units that reside within a single node on an IEEE 1394 bus.

Abstract: The stackable motherboard 10 of the first embodiment includes: a circuit board 19 having a first side 14 and a second side 17 opposite the first side 14, a processor 16 mounted on the circuit board 19, a first peripheral interconnect 18, and a second peripheral interconnect 90. The stackable motherboard 10 also preferably includes: a first motherboard interconnect 99 mounted on the first side 14 of the circuit board 19 and adapted to communicate data between the processor 16 and a first auxiliary motherboard, and a second motherboard interconnect 94 mounted on the second side 17 of the circuit board 19 and adapted to communicate data between the processor 16 and a second auxiliary motherboard.

Abstract: According to one embodiment, a controller for a surveillance system includes ports for coupling a camera, synchronization logic blocks coupled to the ports, an information aggregation logic block coupled to the camera ports, and an output port coupled to the information aggregation logic block. According to another embodiment, a method of scaling a surveillance system includes synchronizing a plurality of cameras, capturing images from the synchronized cameras, aggregating at least two processed synchronized images, and processing the aggregated synchronized images.

Abstract: In one embodiment, the gaming surveillance system includes a camera subsystem, wherein the camera subsystem contains a means for extracting features in real-time, an image server, wherein the image server is connected to the camera subsystem, and communicates with the camera subsystem, and a client connected to the image server, wherein the client receives a data stream from the image server, wherein the data stream includes metadata. In another embodiment, the method of extracting metadata from multiple synchronized cameras includes the steps of capturing a first set of images and a second set of images from multiple synchronized cameras, processing the first set of images and the second set of images, and outputting metadata from the processed image sets.

Abstract: A method of partitioning an algorithm between hardware and software includes accepting a user defined algorithm specified in a source code, identifying worker methods and feature extraction methods within the user defined algorithm, replacing worker methods in the source code with hardware logic, replacing feature extraction methods with a combination of hardware logic and software libraries that interface with the hardware logic, and outputting an FPGA programming specification of the hardware logic and interface libraries.

Abstract: An automated system and method for programming field programmable gate arrays (FPGAs) is disclosed for implementing user-defined algorithms specified in a high level language. The system is particularly suited for use with image processing algorithms and can speed up the process of implementing and testing a fully written high-level user-defined algorithm to a matter of a few minutes, rather than the days, weeks or even months presently required using conventional software tools. The automated system includes an analyzer module and a mapper module. The analyzer determines what logic components are required and their interrelationships, and observes the relative timing between the required components and their partial products. It also ascertains when signal delays are required between selected components.

Abstract: An automated system and method for programming field programmable gate arrays (FPGAs) is disclosed for implementing user-defined algorithms specified in a high level language. The system is particularly suited for use with image processing algorithms and can speed up the process of implementing and testing a fully written high-level user-defined algorithm to a matter of a few minutes, rather than the days, weeks or even months presently required using conventional software tools. The automated system includes an analyzer module and a mapper module. The analyzer determines what logic components are required and their interrelationships, and observes the relative timing between the required components and their partial products. It also ascertains when signal delays are required between selected components.

Abstract: A computer system and a method for a mail sorting operation in which the computer system determines the location of the ZIP code within a digital image of an address block from a piece of mail. An interstroke distance is calculated for the image and the strokes of the image are thinned to enhance vertical separation between the lines of the address block. A medial axis for each line is determined and the medial axis is superimposed upon the digital image. A bleeding operation is conducted on the digital image from the medial axis at which data bits that do not connect to the medial axis are notated as punctuation and interlinear connected strokes are then divided between the two lines. The last line which is determined to be large enough to contain a ZIP code based on bounding box size is then selected. Alternate splits of words are formed and the best split is selected in which the last formed group is detected to be the ZIP code.

Abstract: A computer system and a method for a mail sorting operation in which the computer system determines the location of the ZIP code within a digital image of an address block from a piece of mail. An interstroke distance is calculated for the image and the strokes of the image are thinned to enhance vertical separation between the lines of the address block. A medial axis for each line is determined and the medial axis is superimposed upon the digital image. A bleeding operation is conducted on the digital image from the medial axis at which data bits that do not connect to the medial axis are notated as punctuation and interlinear connected strokes are then divided between the two lines. The last line which is determined to be large enough to contain a ZIP code based on bounding box size is then selected. Alternate splits of words are formed and the best split is selected in which the last formed group is detected to be the ZIP code.

Abstract: A cellular processing system for analyzing an image comprising a matrix of points employs an image memory for storing digital data signals representative of each of the points, a plurality of special function processing units, each adapted to perform a specific operation on one or more images, and data bus means for selectively distributing image data from the image memory to one or more preselected function processors for processing in a cascaded fashion and returning the processed data signals back to image memory. The special function process units include a pipeline processor employing one or more programmable, substantially identical neighborhood transformation stages and an image combiner including means for performing arithmetic, logical, and conditional operations on one or more images.

Abstract: A system for analyzing images represented by a serial stream of digital electrical signals corresponding to values of pixels in a matrix of points constituting an image. The system includes a pipeline of substantially identical neighborhood transformation stages. Each stage includes a processor portion for analyzing the pixel values and a memory portion communicating with the processor portion for sequentially providing a window of neighboring pixels to the processor for analysis. A central programmable controller communicates with the pipeline over a single communication link which provides both the pixel value data to the pipeline and transformation control instructions to the processor portions of each stage. The memory portion preferably includes a random access memory which serves as a line storage device which may be readily adjusted to accommodate different raster scan line lengths from various image sensors.

Abstract: A plurality of serial neighborhood transformation pipelines are provided for simultaneously operating on adjacent segments of a partitioned image matrix. Techniques are disclosed for bi-directionally transferring pixel data on the edges of adjoining segments of the image matrix between adjacent processors in a manner which minimizes the number of interconnections therebetween. In such manner a parallel pipeline image processing system can be implemented in integrated circuit form while keeping the number of pins for each stage in the pipeline to a minimum.

Abstract: An image analyzer system includes a pipeline of individually programmable neighborhood transformation stages. Programming of the stages is accomplished by way of coded command signals which are either of a local or global type. Global commands propagate down the pipeline to all of the stages whereas local commands are utilized to program only selected stages. Once the stages are programmed the image data may be transferred over the same bus previously utilized to carry the programming instructions. In the preferred embodiment, control lines are employed to indicate whether image data or programming instructions are being transferred over the bus.

Abstract: A system for analyzing images represented by a plurality of raster scan lines of pixel values employs at least one neighborhood transformation stage. The stage includes a processor portion for analyzing windows of neighboring pixel values and providing a transformation output as a function of the pixel values contained in the window. A random access memory (RAM) repetitively stores a given plurality of successive pixel scan lines fed to the stage. Selected pixel values from the RAM are loaded into the processor portion so as to sequentially access the neighborhood windows for analysis. The RAM serves as a recirculating line storage device for accommodating different raster scan line lengths.

Abstract: An image analyzer system employs one or more neighborhood transformation stages. The stage operates to access groups of neighboring pixels in an image matrix, analyzes them and generates a transformation output as a result of the analysis. The stage includes a logic circuit which is programmable from a central controller. In the preferred embodiment, each pixel in the neighborhood is analyzed by the logic circuit and temporarily stored until other pixels in the group have been analyzed. The combination of analyzed pixel values form the basis for generating the transformation output for the stage. Preferably, the logic circuit is designed to perform both two dimensional and three dimensional image analyses.

Abstract: An image analyzer system and a method of analyzing image information contained in serial scan lines of pixels in which some of the pixels have valid data values representing image information while other pixels have invalid data values not representing characteristics of the image to be analyzed. Off image detector circuitry is utilized to generate output signals to neighborhood transformation logic when one or more pixels in a neighborhood contain invalid values. Preferably, the off image detector means monitors the status of a control line which indicates whether valid or invalid pixels are being transferred over a bus to a stage of the image analyzer system. The detector circuitry operates to store the number of valid pixels in subsequent scan lines presented to the stage. This comparison is utilized to detect invalid pixel values which may be contained in each neighborhood.