Abstract: Apparatus for measuring skew in a clock signal for processing a video signal includes a cascade connection of a plurality of analog delay elements to which the clock signal is applied. The output connections of each analog delay element is coupled to a data input terminal of a respective storage element. A signal representative of the horizontal synchronizing signal is applied to the storage elements to simultaneously latch signal into the respective storage elements, thereby capturing a representative cycle of the sampling clock signal in the storage elements. Decoding circuitry is coupled to the storage elements for detecting the relative position of the e.g., leading transition of the sampling clock pulse immediately preceding the trailing transition of the horizontal pulse A ratio is calculated indicative of the skew error, which ratio corresponds to the position of the first transition, in units of delay, divided by the duration of the sampling clock period, in units of delay.

Abstract: A digital transversal IIR filter, in which the sum of the magnitudes of a large number of coefficient multipliers (which may be real or complex) is greater than unity, may be stable or it may be unstable. The present invention is directed to (1) a test for stability in such a filter which is simpler and faster than solving a large number of polynomial equations, and (2) the repair of a filter found by this test to be unstable. Specifically, means responsive to the respective gradients of the magnitudes of chirp-z transforms of time-domain multiplier coefficient values within one or more selected localized regions of the complex in-phase (I), quadrature(Q) frequency-domain plane determine that a filter is unstable whenever the gradient of the magnitude values of the chirp-z transform within a selected localized region of the frequency-domain plane indicates that there is a pole in the frequency-domain plane that is located beyond the boundary of a frequency-domain unit circle.

Abstract: A television system including a memory for storing subsampled fields in different sectors corresponding to respective small pictures of a rectangular multi-picture array, includes apparatus for expanding the subsampled fields, preferably to full-screen size, as they are read-out of the memory. When the stored sub-sampled fields correspond to different fields of the same video signal, the arrangement provides for a re-animated version of multi-picture array in a so-called "instant replay" mode of operation.

Abstract: A video processing system includes apparatus for panning and magnifying portions of a source image stored in memory. Viewer control circuitry generates center coordinates of the portion of the image to be displayed and also a magnification factor. Further circuitry, responsive to the center coordinates and the magnification factor, generates starting addresses for reading the appropriate portion of the source image from memory. The system monitors the relative values of the center coordinates and the magnification factor to preclude blanking intervals of the source image from being displayed.

Abstract: A programmable sampled data subsampling system includes a programmable antialias filter which bandlimits the information bandwidth of the signal to be subsampled in accordance with the subsampling rate. The antialias filter includes a recursive filter which scales and combines input samples and delayed combined samples in proportions of K and (1-K) where K is a variable. The variables K are applied to the recursive filter in repeating sequences of N values of K where N is the subsampling factor. Every N.sup.th combined sample is extracted and provided as the subsampled signal.

Abstract: A secondary video signal is sampled, digitized and combined with an in-memory switching signal. The combined digital signal is stored in a random access video memory. The stored signal is read out in synchronism with the synchronizing signal components of a primary video signal. The switching signal is recovered from the output of the memory, and compared with a content code signal to develop a fast switching signal. A video output switch, coupled to receive the primary video signal and the stored secondary video signal and responsive to the fast switching signal, applies an appropriate one of the two input signals to the kinescope to define a secondary inset picture within a large primary picture.

Abstract: Circuitry for aligning the transition of a clock signal to transitions of a horizontal line synchronizing signal includes a series of delay elements which provide a plurality of clock signal phases. The longest phase delay provided by this circuitry is greater than the period of the clock signal. The clock signal and the delayed clock signal phases are applied to circuitry which selects one clock signal phase, which has a transition occurring within a predetermined time interval of the transition in the horizontal line synchronizing signal. Other circuitry, coupled to this selection circuitry, inhibits the selection of any clock phase having a greater time delay than the selected phase. This prevents the selection of multiple clock phase signals.

Abstract: An adaptive luma/chroma separation apparatus is herein disclosed. Means, including delay elements and bandpass filters, are employed to generate a set of three bandpassed signals B.sub.b, M.sub.b and T.sub.b, which are delayed with respect to each other by one horizontal line period. A control signal generating circuit coupled to receive the three bandpassed signals B.sub.b, M.sub.b and T.sub.b develops a control signal K that determines the relative mixing of the signals. A combining circuit, including a soft switch, combines the three bandpassed signals in response to the control signal K to generate a separated chroma signal C.sub.b. The separated chroma signal C.sub.b is subtracted from the (non-bandpassed) main signal M to generate the luma signal Y.

Abstract: A video features processor for use with a display device includes a first clock that is line locked to the display and a skew-shifted second clock that is phase locked to the horizontal sync component of an auxiliary video signal. An A/D converter, responsive to the skew-shifted clock, develops digital samples representative of the auxiliary video signal. A clock transfer circuit, responsive to the line-locked and skew-shifted clocks, translates digital samples occurring synchronously with the skew-shifted clock signal to digital samples occurring synchronously with the line-locked clock signal. The digital samples occurring synchronously with the line-locked clock signal are stored in a memory.

Abstract: An arrangement is provided for computing the magnitude value of the vector sum of two quadrature-related component signals I and Q with a minimal of hardware. To this end, the magnitude values of the orthogonal I and Q signals are applied to a ROM as address codes to produce the Log.sub.B .vertline.I.vertline. and Log.sub.B .vertline.Q.vertline. values to the logarithmic base B. The smaller of the Log.sub.B .vertline.I.vertline. and Log.sub.B .vertline.Q.vertline. logarithmic values is subtracted from the larger of the logarithmic values to produce the absolute value .vertline.D.vertline. of the difference between the respective logarithmic values. The difference value D is applied to a ROM as an address code which is programmed to generate a correction value F=0.5 Log.sub.B (1+B.sup.-2.vertline.D.vertline.).

Abstract: Comb filtered video signals having reduced artifacts are adaptively produced by circuitry including delay elements for providing a plurality of video signals delayed by integral numbers of horizontal line periods, for example, signals delayed 1H, 2H, 1 field, 1 frame, etc. Signals from pairs of these lines of signals are compared by developing the sums of cross differences of samples spanning the sample point to be filtered to produce a signal indicative of the pairs of lines having the highest degree of signal correlation at that instant. The pair of lines exhibiting highest correlation are selectively applied to signal combining circuits to generate comb filtered luminance and chrominance signals in the conventional manner.

Abstract: A signal overload circuit for use in e.g. a digital TV receiver includes a piecewise linear weighting circuit which weights samples of greater magnitude proportionately more heavily than samples of lesser magnitude. The weighted samples are applied to an accumulator, and the accumulated value over a field interval is compared to an overload reference value to generate an overload output signal which is combined with other gain factors for application as the common gain control signal to a common amplifier. The overload detector is coupled in a feedback loop around the common amplifier. In order not to defeat the function of the other gain factors, the overload detector is programmable and its sensitivity is made responsive to the other gain factors.