Patents by Inventor David L. Medlock

David L. Medlock has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Integrated circuit having critical path voltage scaling and method therefor
    Patent number: 8575962
    Abstract: An integrated circuit comprises logic circuitry having a plurality of signal paths. A signal path of the plurality of signal paths has a propagation delay greater than a propagation delay of any other signal path of the plurality of signal paths. The signal path includes a plurality of components. The plurality of components is provided with a higher power supply voltage than any other signal path of the plurality of signal paths.
    Type: Grant
    Filed: August 29, 2011
    Date of Patent: November 5, 2013
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Jianan Yang, Stephen G. Jamison, David L. Medlock, Gary Waugh
  • INTEGRATED CIRCUIT HAVING CRITICAL PATH VOLTAGE SCALING AND METHOD THEREFOR
    Publication number: 20130049807
    Abstract: An integrated circuit comprises logic circuitry having a plurality of signal paths. A signal path of the plurality of signal paths has a propagation delay greater than a propagation delay of any other signal path of the plurality of signal paths. The signal path includes a plurality of components. The plurality of components is provided with a higher power supply voltage than any other signal path of the plurality of signal paths.
    Type: Application
    Filed: August 29, 2011
    Publication date: February 28, 2013
    Inventors: JIANAN YANG, Stephen G. Jamison, David L. Medlock, Gary Waugh
  • Current limited current reference for non-volatile memory sensing
    Patent number: 5608676
    Abstract: A non-volatile memo includes the reference cells programmed to opposite logic states whose outputs are combined and then equally divided to provide a reference signal to a sense amplifier which is one half of the sum of the signals from a high conductivity data cell and a low conductivity data cell. The non-volatile memory also includes a bias voltage generator which uses a high conductivity non-volatile reference cell for a reference, and which produces a bias voltage which is coupled to current limiting transistors at the inputs of the sense amplifier so that the current into the sense amplifier is limited and therefore limits the power used by the non-volatile memory.
    Type: Grant
    Filed: August 31, 1993
    Date of Patent: March 4, 1997
    Assignee: Crystal Semiconductor Corporation
    Inventors: David L. Medlock, Eric J. Swanson
  • Variable decimation architecture for a delta-sigma analog-to-digital converter
    Patent number: 5157395
    Abstract: An analog-to-digital converter includes a delta-sigma modulator (10), having the output thereof filtered by a digital filter section. The digital filter section includes a first fixed decimation filter (12) followed by a variable decimation filter section (14) and an output low-pass filter section (16), having a fixed decimation ratio. The fixed variable decimation filter section (14) includes a single FIR filter (24) that has data processed therethrough with different sampling rates. A recursive controller (26) receives an external configuration input to determine the number of passes through the filter (24) that are required to provide the desired decimation ratio.
    Type: Grant
    Filed: March 4, 1991
    Date of Patent: October 20, 1992
    Assignee: Crystal Semiconductor Corporation
    Inventors: Bruce Del Signore, Eric J. Swanson, Jeffrey M. Klaas, David L. Medlock