Abstract: An avionic digital signal processing system for a plurality of different types of input sensors such as radar, electro-optical, and electronic warfare that comprises a PI bus operating at 12.5 MHz and a data network subbus operating at 20 MHz. A plurality of array processor groups each having a plurality of 1750 CPU's are controlled over the PI-bus and receive their sensor inputs over the subbus data network. A plurality of general purpose 1750A computers are connected to the PI-bus for communicating control and narrow band information. A distributed operating system resides in the 1750A central processing units and includes provision for re-routing the signal paths in the event of failure of modules.

Abstract: The interface circuit passes data from a first unit running at one clock rate to a second unit running at another clock rate. READY leads from an In control circuuit to an Out control circuit are used to signal when a data word has been loaded by the first unit; and TAKEN leads from the Out control circuit to the In control circuit are used to signal when a data word has been received by the second unit. An anti-Metastable Flip-flop (AMF) is used with each READY lead and each TAKEN lead. Each AMF flip-flop comprises an input latch, an output latch, a decentration driver, and an oscillation suppressor. The decentration driver handles cases in which the output of the input latch is balanced and floating or balanced and driven by tugging the output of the input latch toward a logic 0 soon after an active edge of a signal on the flip-flop clock lead has caused the input latch to close.