Abstract: A method of establishing regions for placing cells of an integrated circuit (IC) includes, in part, assigning a precedence value to each of a multitude of constraint regions of the IC, and forming a multitude regions each associated with one of the constraint regions. The region associated with each constraint region is formed in accordance with the precedence value of its associated constraint region and the precedence values associated with any other constraint regions overlapping the first constraint region. Each region in a subset of the constraint regions is further defined in accordance with the region's transparency/opacity attribute.

Abstract: Methods and apparatuses are described for creating, editing, and viewing a floorplan of a circuit design. Specifically, some embodiments enable a user to perform a graphical operation at an inference point in a circuit design layout, wherein the location of the inference point is determined based on existing graphical objects in the circuit design layout. Some embodiments substantially instantaneously update a congestion indicator in _a circuit design layout in response to modifying the circuit design layout. Some embodiments substantially instantaneously update pin locations of a block or partition in response to changing the size or shape of the block or partition. Some embodiments enable a user to view a circuit design layout based on the logical hierarchy, and also based on at least one additional attribute type such as voltage, power, or clock domain.

Abstract: Embodiments are described in which shaping is integrated with power network synthesis (PNS) for power grid (PG) alignment. Specifically, some embodiments create placement constraints based on the PG that is expected to be created by PNS, and then perform shaping (or perform legalization) on the circuit design based on the placement constraints. This ensures that the physical partitions (e.g., instances of multiply-instantiated-blocks) are aligned with the power grid during shaping.

Abstract: A method of establishing regions for placing cells of an integrated circuit (IC) includes, in part, assigning a precedence value to each of a multitude of constraint regions of the IC, and forming a multitude regions each associated with one of the constraint regions. The region associated with each constraint region is formed in accordance with the precedence value of its associated constraint region and the precedence values associated with any other constraint regions overlapping the first constraint region. Each region in a subset of the constraint regions is further defined in accordance with the region's transparency/opacity attribute.

Abstract: Methods and apparatuses are described for creating, editing, and viewing a floorplan of a circuit design. Specifically, some embodiments enable a user to perform a graphical operation at an inference point in a circuit design layout, wherein the location of the inference point is determined based on existing graphical objects in the circuit design layout. Some embodiments substantially instantaneously update a congestion indicator in _a circuit design layout in response to modifying the circuit design layout. Some embodiments substantially instantaneously update pin locations of a block or partition in response to changing the size or shape of the block or partition. Some embodiments enable a user to view a circuit design layout based on the logical hierarchy, and also based on at least one additional attribute type such as voltage, power, or clock domain.

Abstract: Methods and apparatuses are described for creating, editing, and viewing a floorplan of a circuit design. Specifically, some embodiments enable a user to perform a graphical operation at an inference point in a circuit design layout, wherein the location of the inference point is determined based on existing graphical objects in the circuit design layout. Some embodiments substantially instantaneously update a congestion indicator in a circuit design layout in response to modifying the circuit design layout. Some embodiments substantially instantaneously update pin locations of a block or partition in response to changing the size or shape of the block or partition. Some embodiments enable a user to view a circuit design layout based on the logical hierarchy, and also based on at least one additional attribute type such as voltage, power, or clock domain.

Abstract: Methods and apparatuses are described for creating, editing, and viewing a floorplan of a circuit design. Specifically, some embodiments enable a user to perform a graphical operation at an inference point in a circuit design layout, wherein the location of the inference point is determined based on existing graphical objects in the circuit design layout. Some embodiments substantially instantaneously update a congestion indicator in a circuit design layout in response to modifying the circuit design layout. Some embodiments substantially instantaneously update pin locations of a block or partition in response to changing the size or shape of the block or partition. Some embodiments enable a user to view a circuit design layout based on the logical hierarchy, and also based on at least one additional attribute type such as voltage, power, or clock domain.

Abstract: Embodiments are described in which shaping is integrated with power network synthesis (PNS) for power grid (PG) alignment. Specifically, some embodiments create placement constraints based on the PG that is expected to be created by PNS, and then perform shaping (or perform legalization) on the circuit design based on the placement constraints. This ensures that the physical partitions (e.g., instances of multiply-instantiated-blocks) are aligned with the power grid during shaping.

Abstract: One embodiment provides a system comprising methods and apparatuses that generate a floorplan for a hierarchical circuit design. More specifically, the system can receive a non-reduced netlist description for the hierarchical circuit design, and generate a reduced netlist which includes the interface logic elements of the netlist. The system can then generate the floorplan by using the reduced netlist as input. Note that the amount of computational resources and time required to generate a floorplan is substantially reduced because the system generates the floorplan using the reduced netlist instead of using the non-reduced netlist.

Abstract: One embodiment provides a system comprising methods and apparatuses that generate a floorplan for a hierarchical circuit design. More specifically, the system can receive a non-reduced netlist description for the hierarchical circuit design, and generate a reduced netlist which includes the interface logic elements of the netlist. The system can then generate the floorplan by using the reduced netlist as input. Note that the amount of computational resources and time required to generate a floorplan is substantially reduced because the system generates the floorplan using the reduced netlist instead of using the non-reduced netlist.