Patents by Inventor David L. Rath

David L. Rath has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11857997
    Abstract: Techniques regarding methods and/or apparatuses for protecting metal substrates during one or more lithography processes are provided. For example, one or more embodiments described herein can comprise a method that can include coating a metal substrate with a polymer film that self-assembles on a metal oxide positioned on a surface of the metal substrate. The method can also include covalently bonding the polymer film to the metal oxide.
    Type: Grant
    Filed: June 18, 2020
    Date of Patent: January 2, 2024
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ali Afzali-Ardakani, David L. Rath, Sarunya Bangsaruntip, George Gabriel Totir
  • Patent number: 11575077
    Abstract: A method for fabricating a bridge structure in a quantum mechanical device includes providing a substructure including a substrate having deposited thereon a layer of a first superconducting material divided into a first portion, a second portion and a third portion that are electrically insulated from each other; depositing a sacrificial layer on the substructure; electrically connecting the first portion and the second portion with a strip of a second superconducting material, the second superconducting material being different from the first superconducting material; and removing a portion of the sacrificial layer so as to form a bridge structure over the third portion between the first portion and the second portion, the bridge structure electrically connecting the first portion to the second portion while not electrically connecting the third portion to the first portion and not electrically connecting the third portion to the second portion.
    Type: Grant
    Filed: January 13, 2020
    Date of Patent: February 7, 2023
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Vivekananda P. Adiga, Hongwen Yan, John M. Papalia, David L. Rath, Jyotica Patel
  • Patent number: 11316154
    Abstract: A three dimensional (3D) In-Silicon energy storage device is provided by a method that includes forming a thick dielectric material layer on a surface of a silicon based substrate. A 3D trench is then formed into the dielectric material layer and the silicon based substrate, and thereafter a dielectric material spacer is formed, in addition to the dielectric remaining on the field of the substrate, as well as along a sidewall of the 3D trench, and on a first portion of a sub-surface of the silicon based substrate that is present at a bottom of the 3D trench. A second portion of the sub-surface of the silicon based substrate that is present in the 3D trench remains physically exposed. Active energy storage device materials can then be formed laterally adjacent to the dielectric material spacer that is within the 3D trench and on the dielectric material layer.
    Type: Grant
    Filed: December 3, 2019
    Date of Patent: April 26, 2022
    Assignee: International Business Machines Corporation
    Inventors: John Collins, John M. Papalia, David L. Rath, Devendra K. Sadana
  • Publication number: 20220123195
    Abstract: Devices, systems, methods, and/or computer-implemented methods that can facilitate protection of a substrate in a qubit device using sacrificial material are provided. According to an embodiment, a device can comprise a superconducting lead provided on a pillar of a sacrificial material provided on a substrate. The device can further comprise a collapsed superconducting junction provided on the substrate and coupled to the superconducting lead.
    Type: Application
    Filed: October 15, 2020
    Publication date: April 21, 2022
    Inventors: Vivekananda P. Adiga, Martin S. Sandberg, Jeng-Bang Yau, David L. Rath, John Bruley, Cihan Kurter, Kenneth P. Rodbell, Hongwen Yan
  • Patent number: 11276767
    Abstract: An additive core subtractive liner method is described for forming electrically conductive contacts. The method can include forming a first trench in an first dielectric layer to expose a first portion of a metal liner, and filling said first trench with a second dielectric layer. A metal cut trench is formed in the second dielectric layer. A portion of the metal liner exposed by the metal cut trench is removed with a subtractive method. The method continues with filling the metal cut trench with a dielectric fill, and replacing the remaining portions of the second dielectric layer with an additive core conductor to provide contacts to remaining portions of the metal liner.
    Type: Grant
    Filed: March 15, 2017
    Date of Patent: March 15, 2022
    Assignee: International Business Machines Corporation
    Inventors: Ruqiang Bao, Kisup Chung, Andrew M. Greene, Sivananda K. Kanakasabapathy, David L. Rath, Indira P. V. Seshadri, Rajasekhar Venigalla
  • Publication number: 20210394229
    Abstract: Techniques regarding methods and/or apparatuses for protecting metal substrates during one or more lithography processes are provided. For example, one or more embodiments described herein can comprise a method that can include coating a metal substrate with a polymer film that self-assembles on a metal oxide positioned on a surface of the metal substrate. The method can also include covalently bonding the polymer film to the metal oxide.
    Type: Application
    Filed: June 18, 2020
    Publication date: December 23, 2021
    Inventors: Ali Afzali-Ardakani, David L. Rath, Sarunya Bangsaruntip, George Gabriel Totir
  • Patent number: 11152489
    Abstract: An additive core subtractive liner method is described for forming electrically conductive contacts. The method can include forming a first trench in a first dielectric layer to expose a first portion of a metal liner, and filling said first trench with a second dielectric layer. A metal cut trench is formed in the second dielectric layer. A portion of the metal liner exposed by the metal cut trench is removed with a subtractive method. The method continues with filling the metal cut trench with a dielectric fill, and replacing the remaining portions of the second dielectric layer with an additive core conductor to provide contacts to remaining portions of the metal liner.
    Type: Grant
    Filed: November 12, 2019
    Date of Patent: October 19, 2021
    Assignee: International Business Machines Corporation
    Inventors: Ruqiang Bao, Kisup Chung, Andrew M. Greene, Sivananda K. Kanakasabapathy, David L. Rath, Indira P. V. Seshadri, Rajasekhar Venigalla
  • Patent number: 11094873
    Abstract: A method of making a Josephson junction in a superconducting qubit includes providing a substrate having a convex structure with a first face and a second face meeting at an edge; depositing a first layer of superconducting material on the first face; oxidizing the first layer to form a layer of oxide material on a surface of the first layer; and depositing a second layer of the superconducting material on the second face. A portion of the second layer is in contact with a portion of the layer of oxide material at or in the vicinity of the edge such that the portion of the layer of oxide material is sandwiched between a portion of the first layer and the portion of the second layer to define a Josephson junction at or in the vicinity of the edge.
    Type: Grant
    Filed: November 14, 2019
    Date of Patent: August 17, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Vivekananda Adiga, David L. Rath, Martin O. Sandberg
  • Patent number: 11075281
    Abstract: An additive core subtractive liner method is described for forming electrically conductive contacts. The method can include forming a first trench in a first dielectric layer to expose a first portion of a metal liner, and filling said first trench with a second dielectric layer. A metal cut trench is formed in the second dielectric layer. A portion of the metal liner exposed by the metal cut trench is removed with a subtractive method. The method continues with filling the metal cut trench with a dielectric fill, and replacing the remaining portions of the second dielectric layer with an additive core conductor to provide contacts to remaining portions of the metal liner.
    Type: Grant
    Filed: November 12, 2019
    Date of Patent: July 27, 2021
    Assignee: International Business Machines Corporation
    Inventors: Ruqiang Bao, Kisup Chung, Andrew M. Greene, Sivananda K. Kanakasabapathy, David L. Rath, Indira P. V. Seshadri, Rajasekhar Venigalla
  • Publication number: 20210217947
    Abstract: A method for fabricating a bridge structure in a quantum mechanical device includes providing a substructure including a substrate having deposited thereon a layer of a first superconducting material divided into a first portion, a second portion and a third portion that are electrically insulated from each other; depositing a sacrificial layer on the substructure; electrically connecting the first portion and the second portion with a strip of a second superconducting material, the second superconducting material being different from the first superconducting material; and removing a portion of the sacrificial layer so as to form a bridge structure over the third portion between the first portion and the second portion, the bridge structure electrically connecting the first portion to the second portion while not electrically connecting the third portion to the first portion and not electrically connecting the third portion to the second portion.
    Type: Application
    Filed: January 13, 2020
    Publication date: July 15, 2021
    Inventors: Vivekananda P. Adiga, Hongwen Yan, JOHN M. PAPALIA, David L. Rath, Jyotica Patel
  • Publication number: 20210167370
    Abstract: A three dimensional (3D) In-Silicon energy storage device is provided by a method that includes forming a thick dielectric material layer on a surface of a silicon based substrate. A 3D trench is then formed into the dielectric material layer and the silicon based substrate, and thereafter a dielectric material spacer is formed, in addition to the dielectric remaining on the field of the substrate, as well as along a sidewall of the 3D trench, and on a first portion of a sub-surface of the silicon based substrate that is present at a bottom of the 3D trench. A second portion of the sub-surface of the silicon based substrate that is present in the 3D trench remains physically exposed. Active energy storage device materials can then be formed laterally adjacent to the dielectric material spacer that is within the 3D trench and on the dielectric material layer.
    Type: Application
    Filed: December 3, 2019
    Publication date: June 3, 2021
    Inventors: John Collins, John M. Papalia, David L. Rath, Devendra K. Sadana
  • Patent number: 11024512
    Abstract: Enhanced compositions and methods are provided for selectively etching silicon wafers, which is particularly useful in the context of silicon wafer manufacturing and processing applications. Optionally, a formulation is provided which selectively etches silicon dioxide in preference to aluminum oxide. Optionally, a formulation and method are provided that is substantially non-aqueous.
    Type: Grant
    Filed: March 6, 2020
    Date of Patent: June 1, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ali Afzali-Ardakani, Benjamin Wymore, David L. Rath, George G. Totir
  • Publication number: 20210151659
    Abstract: A method of making a Josephson junction in a superconducting qubit includes providing a substrate having a convex structure with a first face and a second face meeting at an edge; depositing a first layer of superconducting material on the first face; oxidizing the first layer to form a layer of oxide material on a surface of the first layer; and depositing a second layer of the superconducting material on the second face. A portion of the second layer is in contact with a portion of the layer of oxide material at or in the vicinity of the edge such that the portion of the layer of oxide material is sandwiched between a portion of the first layer and the portion of the second layer to define a Josephson junction at or in the vicinity of the edge.
    Type: Application
    Filed: November 14, 2019
    Publication date: May 20, 2021
    Inventors: Vivekananda Adiga, David L. Rath, Martin O. Sandberg
  • Publication number: 20200328156
    Abstract: A low aspect ratio interconnect is provided and includes a metallization layer, a liner and a metallic interconnect. The metallization layer includes bottommost and uppermost surfaces. The uppermost surface has a maximum post-deposition height from the bottommost surface at first metallization layer portions. The metallization layer defines a trench at second metallization layer portions. The liner includes is disposed to line the trench and includes liner sidewalls that have terminal edges that extend to the maximum post-deposition height and lie coplanar with the uppermost surface at the first metallization layer portions. The metallic interconnect is disposed on the liner to fill a trench remainder and has an uppermost interconnect surface that extends to the maximum post-deposition height and lies coplanar with the uppermost surface at the first metallization layer portions.
    Type: Application
    Filed: May 29, 2020
    Publication date: October 15, 2020
    Inventors: Benjamin D. Briggs, Elbert Huang, Raghuveer R. Patlolla, Cornelius Brown Peethala, David L. Rath, Chih-Chao Yang
  • Patent number: 10672707
    Abstract: A low aspect ratio interconnect is provided and includes a metallization layer, a liner and a metallic interconnect. The metallization layer includes bottommost and uppermost surfaces. The uppermost surface has a maximum post-deposition height from the bottommost surface at first metallization layer portions. The metallization layer defines a trench at second metallization layer portions. The liner includes is disposed to line the trench and includes liner sidewalls that have terminal edges that extend to the maximum post-deposition height and lie coplanar with the uppermost surface at the first metallization layer portions. The metallic interconnect is disposed on the liner to fill a trench remainder and has an uppermost interconnect surface that extends to the maximum post-deposition height and lies coplanar with the uppermost surface at the first metallization layer portions.
    Type: Grant
    Filed: January 17, 2019
    Date of Patent: June 2, 2020
    Assignee: Tessera, Inc.
    Inventors: Benjamin D. Briggs, Elbert E. Huang, Raghuveer R. Patlolla, Cornelius Brown Peethala, David L. Rath, Chih-Chao Yang
  • Patent number: 10607933
    Abstract: A structure having fully aligned via connecting metal lines on different Mx levels. The structure may include a first metal line and a second metal line in a first ILD, a cap covering the first ILD, the second metal line and a portion of the first metal line, a second ILD on the cap, and a via that electrically connects the first metal line to a third metal line, wherein the third metal line is above the first metal line and runs perpendicular to the first metal line, the via is fully aligned to the first metal line and the third metal line, and the via electrically connects the first metal line to the third metal line.
    Type: Grant
    Filed: January 2, 2019
    Date of Patent: March 31, 2020
    Assignee: International Business Machines Corporation
    Inventors: Daniel C. Edelstein, Nicholas C. Fuller, Elbert E. Huang, Satyanarayana V. Nitta, David L. Rath
  • Patent number: 10600884
    Abstract: An additive core subtractive liner method is described for forming electrically conductive contacts. The method can include forming a first trench in an first dielectric layer to expose a first portion of a metal liner, and filling said first trench with a second dielectric layer. A metal cut trench is formed in the second dielectric layer. A portion of the metal liner exposed by the metal cut trench is removed with a subtractive method. The method continues with filling the metal cut trench with a dielectric fill, and replacing the remaining portions of the second dielectric layer with an additive core conductor to provide contacts to remaining portions of the metal liner.
    Type: Grant
    Filed: December 5, 2017
    Date of Patent: March 24, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ruqiang Bao, Kisup Chung, Andrew M. Greene, Sivananda K. Kanakasabapathy, David L. Rath, Indira P. V. Seshadri, Rajasekhar Venigalla
  • Publication number: 20200083349
    Abstract: An additive core subtractive liner method is described for forming electrically conductive contacts. The method can include forming a first trench in a first dielectric layer to expose a first portion of a metal liner, and filling said first trench with a second dielectric layer. A metal cut trench is formed in the second dielectric layer. A portion of the metal liner exposed by the metal cut trench is removed with a subtractive method.
    Type: Application
    Filed: November 12, 2019
    Publication date: March 12, 2020
    Inventors: Ruqiang Bao, Kisup Chung, Andrew M. Greene, Sivananda K. Kanakasabapathy, David L. Rath, Indira P.V. Seshadri, Rajasekhar Venigalla
  • Publication number: 20200083350
    Abstract: An additive core subtractive liner method is described for forming electrically conductive contacts. The method can include forming a first trench in a first dielectric layer to expose a first portion of a metal liner, and filling said first trench with a second dielectric layer. A metal cut trench is formed in the second dielectric layer. A portion of the metal liner exposed by the metal cut trench is removed with a subtractive method.
    Type: Application
    Filed: November 12, 2019
    Publication date: March 12, 2020
    Inventors: Ruqiang Bao, Kisup Chung, Andrew M. Greene, Sivananda K. Kanakasabapathy, David L. Rath, Indira P.V. Seshadri, Rajasekhar Venigalla
  • Publication number: 20190157201
    Abstract: A structure having fully aligned via connecting metal lines on different Mx levels. The structure may include a first metal line and a second metal line in a first ILD, a cap covering the first ILD, the second metal line and a portion of the first metal line, a second ILD on the cap, and a via that electrically connects the first metal line to a third metal line, wherein the third metal line is above the first metal line and runs perpendicular to the first metal line, the via is fully aligned to the first metal line and the third metal line, and the via electrically connects the first metal line to the third metal line.
    Type: Application
    Filed: January 2, 2019
    Publication date: May 23, 2019
    Inventors: Daniel C. Edelstein, Nicholas C. Fuller, Elbert E. Huang, Satyanarayana V. Nitta, David L. Rath