Patents by Inventor David L. Satterfield

David L. Satterfield has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • DISTRIBUTED TRACE USING CENTRAL PERFORMANCE COUNTER MEMORY
    Publication number: 20120324138
    Abstract: A plurality of processing cores, are central storage unit having at least memory connected in a daisy chain manner, forming a daisy chain ring layout on an integrated chip. At least one of the plurality of processing cores places trace data on the daisy chain connection for transmitting the trace data to the central storage unit, and the central storage unit detects the trace data and stores the trace data in the memory co-located in with the central storage unit.
    Type: Application
    Filed: August 21, 2012
    Publication date: December 20, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: David L. Satterfield, James C. Sexton
  • MULTI-PETASCALE HIGHLY EFFICIENT PARALLEL SUPERCOMPUTER
    Publication number: 20110219208
    Abstract: A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaOPS-scale computing, at decreased cost, power and footprint, and that allows for a maximum packaging density of processing nodes from an interconnect point of view. The Supercomputer exploits technological advances in VLSI that enables a computing model where many processors can be integrated into a single Application Specific Integrated Circuit (ASIC).
    Type: Application
    Filed: January 10, 2011
    Publication date: September 8, 2011
    Applicant: International Business Machines Corporation
    Inventors: Sameh Asaad, Ralph E. Bellofatto, Michael A. Blocksome, Matthias A. Blumrich, Peter Boyle, Jose R. Brunheroto, Dong Chen, Chen-Yong Cher, George L. Chiu, Norman Christ, Paul W. Coteus, Kristan D. Davis, Gabor J. Dozsa, Alexandre E. Eichenberger, Noel A. Eisley, Matthew R. Ellavsky, Kahn C. Evans, Bruce M. Fleischer, Thomas W. Fox, Alan Gara, Mark E. Giampapa, Thomas M. Gooding, Michael K. Gschwind, John A. Gunnels, Shawn A. Hall, Rudolf A. Haring, Philip Heidelberger, Todd A. Inglett, Brant L. Knudson, Gerard V. Kopcsay, Sameer Kumar, Amith R. Mamidala, James A. Marcella, Mark G. Megerian, Douglas R. Miller, Samuel J. Miller, Adam J. Muff, Michael B. Mundy, John K. O'Brien, Kathryn M. O'Brien, Martin Ohmacht, Jeffrey J. Parker, Ruth J. Poole, Joseph D. Ratterman, Valentina Salapura, David L. Satterfield, Robert M. Senger, Brian Smith, Burkhard Steinmacher-Burow, William M. Stockdell, Craig B. Stunkel, Krishnan Sugavanam, Yutaka Sugawara, Todd E. Takken, Barry M. Trager, James L. Van Oosten, Charles D. Wait, Robert E. Walkup, Alfred T. Watson, Robert W. Wisniewski, Peng Wu
  • DISTRIBUTED TRACE USING CENTRAL PERFORMANCE COUNTER MEMORY
    Publication number: 20110173366
    Abstract: A plurality of processing cores, are central storage unit having at least memory connected in a daisy chain manner, forming a daisy chain ring layout on an integrated chip. At least one of the plurality of processing cores places trace data on the daisy chain connection for transmitting the trace data to the central storage unit, and the central storage unit detects the trace data and stores the trace data in the memory co-located in with the central storage unit.
    Type: Application
    Filed: January 8, 2010
    Publication date: July 14, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: David L. Satterfield, James C. Sexton
  • OPCODE COUNTING FOR PERFORMANCE MEASUREMENT
    Publication number: 20110172969
    Abstract: Methods, systems and computer program products are disclosed for measuring a performance of a program running on a processing unit of a processing system. In one embodiment, the method comprises informing a logic unit of each instruction in the program that is executed by the processing unit, assigning a weight to each instruction, assigning the instructions to a plurality of groups, and analyzing the plurality of groups to measure one or more metrics. In one embodiment, each instruction includes an operating code portion, and the assigning includes assigning the instructions to the groups based on the operating code portions of the instructions. In an embodiment, each type of instruction is assigned to a respective one of the plurality of groups. These groups may be combined into a plurality of sets of the groups.
    Type: Application
    Filed: January 15, 2010
    Publication date: July 14, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Alan Gara, David L. Satterfield, Robert E. Walkup
  • DISTRIBUTED PERFORMANCE COUNTERS
    Publication number: 20110172968
    Abstract: A plurality of first performance counter modules is coupled to a plurality of processing cores. The plurality of first performance counter modules is operable to collect performance data associated with the plurality of processing cores respectively. A plurality of second performance counter modules are coupled to a plurality of L2 cache units, and the plurality of second performance counter modules are operable to collect performance data associated with the plurality of L2 cache units respectively. A central performance counter module may be operable to coordinate counter data from the plurality of first performance counter modules and the plurality of second performance modules, the a central performance counter module, the plurality of first performance counter modules, and the plurality of second performance counter modules connected by a daisy chain connection.
    Type: Application
    Filed: January 8, 2010
    Publication date: July 14, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kristan D. Davis, Kahn C. Evans, Alan Gara, David L. Satterfield
  • PROCESSOR RESUME UNIT
    Publication number: 20110173420
    Abstract: A system for enhancing performance of a computer includes a computer system having a data storage device. The computer system includes a program stored in the data storage device and steps of the program are executed by a processor. An external unit is external to the processor for monitoring specified computer resources. The external unit is configured to detect a specified condition using the processor. The processor including one or more threads. The thread resumes an active state from a pause state using the external unit when the specified condition is detected by the external unit.
    Type: Application
    Filed: January 8, 2010
    Publication date: July 14, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Dong Chen, Mark Giampapa, Philip Heidelberger, Martin Ohmacht, David L. Satterfield, Burkhard Steinmacher-Burow, Krishnan Sugavanam
  • PAUSE PROCESSOR HARDWARE THREAD UNTIL PIN
    Publication number: 20110173422
    Abstract: A system and method for enhancing performance of a computer which includes a computer system including a data storage device. The computer system includes a program stored in the data storage device and steps of the program are executed by a processer. The processor processes instructions from the program. A wait state in the processor waits for receiving specified data. A thread in the processor has a pause state wherein the processor waits for specified data. A pin in the processor initiates a return to an active state from the pause state for the thread. A logic circuit is external to the processor, and the logic circuit is configured to detect a specified condition. The pin initiates a return to the active state of the thread when the specified condition is detected using the logic circuit.
    Type: Application
    Filed: January 8, 2010
    Publication date: July 14, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Dong Chen, Mark Giampapa, Philip Heidelberger, Martin Ohmacht, David L. Satterfield, Burkhard Steinmacher-Burow, Krishnan Sugavanam
  • HEAP/STACK GUARD PAGES USING A WAKEUP UNIT
    Publication number: 20110119445
    Abstract: A method and system for providing a memory access check on a processor including the steps of detecting accesses to a memory device including level-1 cache using a wakeup unit. The method includes invalidating level-1 cache ranges corresponding to a guard page, and configuring a plurality of wakeup address compare (WAC) registers to allow access to selected WAC registers. The method selects one of the plurality of WAC registers, and sets up a WAC register related to the guard page. The method configures the wakeup unit to interrupt on access of the selected WAC register. The method detects access of the memory device using the wakeup unit when a guard page is violated. The method generates an interrupt to the core using the wakeup unit, and determines the source of the interrupt. The method detects the activated WAC registers assigned to the violated guard page, and initiates a response.
    Type: Application
    Filed: January 29, 2010
    Publication date: May 19, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Thomas M. Gooding, David L. Satterfield, Burkhard Steinmacher-Burow
  • Automatic link failover in data networks
    Patent number: 7042837
    Abstract: Methods and apparatus are disclosed for enabling nodes in a data network having interconnect links to continue to transmit data when a link fails. This is done in realtime, in a manner transparent to upper-level clients, and at a hardware level without software intervention. A method is described in which a data packet is received or stored in a transmitter buffer at an originating node having a failed link where the data packet is scheduled to use the failed link. The data packet is routed to a failover storage area. The failover storage area is a shared resource in the node and consists of two first-in, first-out stacks for processing and routing the failover data packets. If needed, an alternative link is selected for the data packet and the data packet is routed to a transmitter associated with the alternative link. An alternative link is selected using a primary and secondary routing table, also part of the shared resource of the node.
    Type: Grant
    Filed: October 25, 2000
    Date of Patent: May 9, 2006
    Assignee: Sun Microsystems, Inc.
    Inventors: Daniel R. Cassiday, David L. Satterfield
  • High performance transmission link and interconnect
    Patent number: 6952419
    Abstract: Methods and components in an interconnect system for improving the performance of the system with respect to increasing bandwidth in a serial link, increasing the processing speed of a packet in a node, and improving the calibration of links in the system are described. In one aspect of the present invention, a method of encoding framing data in a packet such that less than the normal number of framing bits is required. For example, a flit, the data unit sent over a serial link in one clock cycle, can be 88 bits in length, and a packet can be made up of one, two, or four flits. If the packet is a one- flit packet, two framing bits are inserted into the packet. If the packet is two flits, four framing bits are inserted into the packet, and if it is a four-flit packet, eight framing bits are inserted.
    Type: Grant
    Filed: October 25, 2000
    Date of Patent: October 4, 2005
    Assignee: Sun Microsystems, Inc.
    Inventors: Daniel R. Cassiday, David L. Satterfield
  • Method for superimposing a sequence number in an error detection code in a data network
    Patent number: 6931581
    Abstract: A system and method for superimposing a sequence number of a packet into the CRC segment of the packet thereby allowing more bandwidth in the payload portion of the packet for carrying data is described. Also described is a method of acquiring additional information on the type of error in a packet, e.g., data transmission errors or sequence errors, from analyzing a CRC error. For example, a reported CRC error can be the result of the receipt of a packet with a sequence number the receiver is not expecting (which is a normal occurrence on transmission links due to transmitters resending packets that a receiver has already accepted) or can result from a real error in the transmission of a packet. A first error code check (CRC) value is calculated for the payload segment of a data packet. A second CRC value is calculated for the sequence number of the data packet. The first CRC value and the second CRC value are combined thereby creating a third CRC value.
    Type: Grant
    Filed: October 25, 2000
    Date of Patent: August 16, 2005
    Assignee: Sun Microsystems, Inc.
    Inventors: Daniel R. Cassiday, Randall D. Rettberg, David L. Satterfield, Thomas J. Moser
  • Method for detecting errors on parallel links
    Patent number: 6684363
    Abstract: System and method for rapidly calculating CRC values for messages including encoded bits is described. Tabularized CRC values are used in combination with a logical grid to quickly determine an appropriate CRC value of a message. This determination can take into account encoded inversion bits in the message. A collection of pre-calculated CRC values are arranged in a single-column table and then implemented with selected bits of a message by superimposing the bits in each CRC value onto a logical grid. Vertical lines of the grid are associated with 30 exclusive OR (XOR) gates and horizontal lines are associated with bits in an 88-bit message (or the 30 bits of a CRC value or with 8 bits of a sequence number). Through this grid, the inputs to the XOR gates are determined, thereby facilitating rapid calculations of CRC values due to the high processing speeds possible in XOR gates.
    Type: Grant
    Filed: October 25, 2000
    Date of Patent: January 27, 2004
    Assignee: Sun Microsystems, Inc.
    Inventors: Daniel R. Cassiday, Randall D. Rettberg, David L. Satterfield, Thomas J. Moser
  • Synchronization system and method for plesiochronous signaling
    Patent number: 5799175
    Abstract: An information transfer system transfers information, in the form of at least one digital data word, from an source operating in a first clock signal domain defined by a first clock signal, to a destination operating in a second clock signal domain defined by a second clock signal. The information transfer system includes a buffer, a buffer storage element, a buffer retrieval element and a synchronizer. The buffer storage element stores the data word in the buffer under control of a data word present indication, and the buffer retrieval element retrieves the data word from the buffer under control of the second clock signal and a synchronized data word present indication. The synchronizer generates the synchronized data word present indication in response to the first clock signal, the second clock signal, and the data word present indication, thereby to synchronize the data word present indication from the first clock signal domain into the second clock signal domain.
    Type: Grant
    Filed: July 1, 1996
    Date of Patent: August 25, 1998
    Assignee: Sun Microsystems, Inc.
    Inventors: Daniel R. Cassiday, David L. Satterfield
  • Input/output system for parallel computer for performing parallel file transfers between selected number of input/output devices and another selected number of processing nodes
    Patent number: 5361363
    Abstract: A computer comprising a plurality of processing elements and an input/output processor interconnected by a routing network. The routing network transfers messages between the processing elements and the input/output processor. The processing elements perform processing operations in connection with data received from the input/output processor in messages transferred over the routing network and transferring processed data to the input/output processor in messages over the routing network, the processing elements being connected as a first selected series of leaf nodes. The input/output processor includes a plurality of input/output buffers connected as a second selected series of leaf nodes of the routing network for generating messages for transfer over the routing network to a series of processing elements forming at least a selected subset of the processing elements during an input/output operation.
    Type: Grant
    Filed: August 16, 1991
    Date of Patent: November 1, 1994
    Assignee: Thinking Machines Corporation
    Inventors: David Wells, James P. Tardiff, David L. Satterfield, Eric L. Rowe, Marshall Isman
  • High performance communications interface for multiplexing a plurality of computers to a high performance point to point communications bus
    Patent number: 5222216
    Abstract: A high performance communications interface device for connecting a high speed computer to a high performance communications bus. The high performance communications interface device includes a high performance communications interface device processor, a source interface, a destination interface and at least one I/O processor which controls the transfer of data to the high speed computer from the high performance communications bus and from the high speed computer to the high performance communications bus.
    Type: Grant
    Filed: July 12, 1991
    Date of Patent: June 22, 1993
    Assignee: Thinking Machines Corporation
    Inventors: Edward C. Parish, Robert A. Doolittle, Sharon E. Gillett, Thomas J. Moser, William A. Nesheim, David L. Satterfield, James P. Tardiff