Patents by Inventor David L. Sprague

David L. Sprague has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10867713
    Abstract: Chimneys include several combinable parts useable in nuclear reactors. The parts are modular and removably joinable without destruction for use in directing flow in an operating nuclear reactor and directly fit in storage area during non-operation. Chimney parts are joinable through flanges and connecting structures. Chimney parts may include partitions that divide or direct energetic coolant flow from a nuclear core as well as steam separating and drying structures. The parts each individually fit within storage areas of the nuclear plant, including equipment or buffer pools in the refueling floor of the plant. Methods move the chimney parts between the reactor and storage areas, and multiple parts may be stacked or nested in such moves. Methods are useable underwater and with storage pools to prevent exposure of chimney parts during an outage. During operation, chimneys are useable in place of existing single-piece chimneys.
    Type: Grant
    Filed: October 22, 2018
    Date of Patent: December 15, 2020
    Assignee: GE-HITACHI NUCLEAR ENERGY AMERICAS LLC
    Inventors: Robin D. Sprague, Gerald A. Deaver, David A. Rickard, David L. Major
  • Patent number: 7320105
    Abstract: Apparatus, software and method for displaying line-formatted materials in multiple columns of a screen display and providing for scrolling through the materials such that lines spill from one column to another, are disclosed. The columns form a display area for display of contiguous lines of the line-formatted materials, wherein diagonally opposite ends of the rightmost and leftmost columns define the starting and ending lines of the display area, such that when scrolling through line-formatted materials the lines flow into and out of the display area at the starting and ending lines. In another embodiment, Scripting language encoded line-formatted materials are displayed under the control of a web browser using the scrollable columns. In another embodiment, line-formatted materials are encoded with one or more Scripting language codes that specify to a web browser that the line-formatted materials are to be displayed in scrollable columns.
    Type: Grant
    Filed: August 9, 1999
    Date of Patent: January 15, 2008
    Assignee: Intel Corporation
    Inventors: Igor Sinyak, David L. Sprague
  • Patent number: 6229790
    Abstract: A central controller, such as an RF distribution shelf (RFDS) of a hybrid fiber/coax (HFC) access system, keeps track of the different channels assigned to different remote units, such as the network interface units (NIUs) of the HFC system. Information about the different channel assignments (e.g., for upstream channels) is broadcast to the remote units as part of the overhead bits in each of the downstream channels. Each remote unit monitors the broadcast messages and, over time, updates its own version of the data structure containing the channel assignments, as appropriate. In one embodiment, the central controller also transmits a second type of broadcast message indicating when changes in the channel assignments occur.
    Type: Grant
    Filed: January 29, 1998
    Date of Patent: May 8, 2001
    Assignee: Lucent Technologies Inc.
    Inventors: Alexis M. Butrym, Michael W. Goodwin, Kyoo J. Lee, David L. Sprague, Stuart Warmink
  • Patent number: 6098956
    Abstract: An electrically operated drain valve for recreational vehicles economically fabricated primarily of synthetic plastic parts which is relatively free of corrosion at critical areas and readily retrofitted to existing recreational vehicle drain systems. A housing containing a geared reversible electric motor operating a linear displaceable rack associated with the drain valve operator permits the drain valve to be displaced between open and closed positions.
    Type: Grant
    Filed: May 7, 1997
    Date of Patent: August 8, 2000
    Assignee: Barker Manufacturing Company, Inc.
    Inventor: David L. Sprague, II
  • Patent number: 6018348
    Abstract: A method is disclosed for determining whether a distant 3-dimensional object is completely obstructed from view by a closer 3-dimensional object. The method includes determining which of the two 3-dimensional objects is farther from a viewer. For the object farther away, determining that object's smallest bounding sphere, and projecting that sphere onto the view plane of the observer. For the object closer to the observer, determining that object's largest bounded sphere, and projecting that sphere onto the view plane. The two projections are then compared. If the near-object projection completely contains the far-object projection, then the distant object is completely obscured from view by the closer object. If completely obscured from view, the distant object is discarded; otherwise, the distant object is rendered in the normal manner.
    Type: Grant
    Filed: December 31, 1997
    Date of Patent: January 25, 2000
    Assignee: Intel Corporation
    Inventor: David L. Sprague
  • Patent number: 5870744
    Abstract: A virtual people networking allows multiple people working for the same organizational organization with similar interests to automatically interface with each other when any one of the people accesses any given one of multiple electronic sites provided through an intranet of the organization. A virtual people networking (VPN) module of the present invention is capable of residing in a storage element coupled to a processor running the VPN module in any one of the multiple systems interconnected within the electronic intra-organizational network. The VPN modules may also reside in a storage element coupled to a processor running the VPN module in a firewall system acting as a gateway between the organizational intranet and the Internet providing access to the World Wide Web (WWW).
    Type: Grant
    Filed: June 30, 1997
    Date of Patent: February 9, 1999
    Assignee: Intel Corporation
    Inventor: David L. Sprague
  • Patent number: 5699458
    Abstract: A computer-implemented method and system for browsing encoded images. According to a preferred embodiment, at least one image is encoded with an encoding system to provide at least one encoded image. The encoding includes transforming images of the at least one image in accordance with a transform to provide a plurality of transform coefficients. A subset of the plurality of transform coefficients corresponding to a selected image is transmitted to a remote computer system, wherein the subset of the plurality of transform coefficients corresponds to a low quality version of the selected image.
    Type: Grant
    Filed: June 29, 1995
    Date of Patent: December 16, 1997
    Assignee: Intel Corporation
    Inventor: David L. Sprague
  • Patent number: 5646696
    Abstract: A pixel interpolation system provides for continuous scaling of an image, thus allowing for continuous modification of the size and aspect ratio of the image. A one-dimensional interpolator provides a weighted interpolation between two input pixels using a specified current interpolation weight. The weighting factor is then incrementally changed and further interpolations are sequentially performed across at least one dimension of the image. With one implementation of the system, the scaling across the image remains uniform while the weight varies from one pixel to the next to keep scaling constant. The interpolation operation of this invention may be performed simultaneously both vertically and horizontally.
    Type: Grant
    Filed: May 28, 1996
    Date of Patent: July 8, 1997
    Assignee: Intel Corporation
    Inventor: David L. Sprague
  • Patent number: 5640528
    Abstract: A method and apparatus for translating a first address in a first address space, such as a processor address space, to a second address in a second address space, such as a system address space, are described. Data alignment signal determinations based on comparisons between destination and source addresses permit automatic replacement of virtual addresses with actual physical addresses to permit direct data transfer between devices. In one embodiment, the apparatus for translating comprises a processor; a page table having a mask register, a comparison value register, and a replacement value register; and a comparator coupled to the comparison value register and to the replacement value register. A programmable mask within the translation mask register is employed to partition a virtual address. A first subaddress comprises a subset of the bits of the first address and a second subaddress comprises remaining bits of the first address.
    Type: Grant
    Filed: June 6, 1995
    Date of Patent: June 17, 1997
    Assignee: Intel Corporation
    Inventors: Kevin Harney, David L. Sprague
  • Patent number: 5548793
    Abstract: A system and method for arbitrating among memory requests. According to a preferred embodiment, the system comprises a global memory and a plurality of datapaths. Each datapath comprises a datapath processor for executing instructions of an instruction sequence and for providing a plurality of memory request signal types in accordance with the instructions, wherein the plurality of memory request signal types comprises instruction memory request signals, scalar memory request signals, first-in and first-out memory request signals, statistical decoder memory request signals, and block transfer memory request signals. Each datapath also comprises local memory, a global port for transferring data between the local memory and the global memory, and a dual port comprising first and second local ports for transferring data between the local memory and the datapath processor, wherein the first and second local ports permit simultaneous transfer of data between the local memory and the datapath processor.
    Type: Grant
    Filed: April 21, 1994
    Date of Patent: August 20, 1996
    Assignee: Intel Corporation
    Inventors: David L. Sprague, Kevin Harney, Eiichi Kowashi, Michael Keith, Allen H. Simon, Gregory M. Papadopoulos, Walter P. Hays, George F. Salem, Shih-Wei Shiue, Anthony P. Bertapelli, Vitaly H. Shilman
  • Patent number: 5530884
    Abstract: A method and apparatus for processing data. According to a preferred embodiment, the apparatus comprises a plurality of datapaths, each datapath comprising datapath processor, and a statistical decoder input channel device. The statistical decoder input channel device prefetches variable length encoded data from a variable length encoded data source in response to a request by a program running on a datapath processor of a datapath of the plurality of datapaths. The statistical decoder input channel device comprises a statistical decoder processor and memory for decoding the variable length encoded data to provide fixed length decoded data, and a transmission output channel for transmitting the fixed length decoded data to the datapath.
    Type: Grant
    Filed: April 21, 1994
    Date of Patent: June 25, 1996
    Assignee: Intel Corporation
    Inventors: David L. Sprague, Kevin Harney, Eiichi Kowashi, Michael Keith, Allen H. Simon, Gregory M. Papadopoulos, Walter P. Hays, George F. Salem, Shih-Wei Shiue, Anthony P. Bertapelli, Vitaly H. Shilman
  • Patent number: 5517665
    Abstract: A system and method for processing data. According to a preferred embodiment, the system comprises a global memory and a plurality of datapaths. Each datapath comprises a datapath processor for executing instructions of an instruction sequence and for providing a plurality of memory request signal types in accordance with the instructions, local memory, a global port for transferring data between the local memory and the global memory, and a dual port comprising first and second local ports for transferring data between the local memory and the datapath processor, wherein the first and second local ports permit simultaneous transfer of data between the local memory and the datapath processor.
    Type: Grant
    Filed: April 21, 1994
    Date of Patent: May 14, 1996
    Assignee: Intel Corporation
    Inventors: David L. Sprague, Kevin Harney, Eiichi Kowashi, Michael Keith, Allen H. Simon, Gregory M. Papadopoulos, Walter P. Hays, George F. Salem, Shih-Wei Shiue, Anthony P. Bertapelli, Vitaly H. Shilman
  • Patent number: 5469222
    Abstract: A method and pixel interpolation system for non-linear interpolation of images having a plurality of input pixels and pixel positions. According to a preferred embodiment of the invention, a plurality of pairs of input pixels and a sequence of corresponding interpolation weights are received with a one-dimensional interpolator. A plurality of sequential weighted sums of the pairs of input pixels are provided at a plurality of the pixel positions in accordance with the interpolation weights. The sequence of interpolation weights is provided, where differences between pairs of successive interpolation weights of the sequence of interpolation weights differ. The sequence of interpolation weights is applied to the one-dimensional interpolator.
    Type: Grant
    Filed: June 30, 1993
    Date of Patent: November 21, 1995
    Assignee: Intel Corporation
    Inventor: David L. Sprague
  • Patent number: 5430854
    Abstract: A data processing system having execution units for executing instruction sequences determines at least two conditionals in accordance with the instructions and sets respective flags according to the determined conditionals. These flags are stored and later retrieved sequentially and the execution unit executes selected instructions of the instruction sequence according to the sequentially retrieved mask flags. These masked flags may be stored sequentially in a stack for sequential retrieval at a later time.
    Type: Grant
    Filed: October 27, 1993
    Date of Patent: July 4, 1995
    Inventors: David L. Sprague, Kevin Harney, Eiichi Kowashi, Michael Keith, Allen H. Simon, Michael Papadopoulos, Walter P. Hays, George F. Salem, Shih-Wei Shiue, Anthony P. Bertapelli, Vitaly H. Shilman
  • Patent number: 5384904
    Abstract: A method for performing scaling of a video image uses a noninteger scale factor. The scaling using a series of images scaled according to integer powers of two. An integer scale factor is applied to the image to be scaled in order to provide a series of scaled images. A determination is made which scaled image is the closest image to the one corresponding to the fractional scale factor. The scaled image selected in this manner is then operated upon using an interpolation to obtain the value corresponding to the fractional scale factor. Alternatively, the two scaled images which are closest to the image corresponding to the fractional scale factor may be selected and an interpolation operation or an averaging operation of the two scaled images may be performed to obtain the factional scale image. The scaled images may be predetermined during off-line operations so that a plurality of image selections may be performed upon the same set of predetermined scaled images.
    Type: Grant
    Filed: December 8, 1992
    Date of Patent: January 24, 1995
    Assignee: Intel Corporation
    Inventors: David L. Sprague, Michael Keith
  • Patent number: 5361370
    Abstract: A single-instruction multiple-data video signal processor employs a dual-ported local memory architecture in each local memory including a dedicated port for transfers between the local memory and a global memory. A block transfer controller, in combination with the dedicated port, permit each access to the global memory by a datapath processor to be overlapped with its instruction processing, thus usually avoiding stalling of the video signal processor.
    Type: Grant
    Filed: October 24, 1991
    Date of Patent: November 1, 1994
    Assignee: Intel Corporation
    Inventors: David L. Sprague, Kevin Harney, Eiichi Kowashi, Michael Keith, Allen H. Simon, Michael Papadopoulos, Walter P. Hays, George F. Salem, Shih-Wei Shiue, Anthony P. Bertapellil, Vitaly H. Shilman
  • Patent number: 5303290
    Abstract: This application discloses a system for eliminating a busy line condition and completing a call over a virtual private line when the stations at each of the lines attempt to initiate a call simultaneously. The system is implemented in three phases. In a first phase, the busy line condition is detected by either the communication switching system which sets up the virtual private line or by two signal converters, each connected to a station set at each end of the line. In a second phase, the switching system or the converters send terminating supervisory signals towards each station to terminate the attempted initial calls while the stations are still off-hook. In a third phase, a predetermined signal converter or a selected switch in the communication switching system initiates a new call by emitting an originating supervisory signal while the stations are still off-hook.
    Type: Grant
    Filed: November 29, 1991
    Date of Patent: April 12, 1994
    Assignee: AT&T Bell Laboratories
    Inventors: David A. Redberg, David L. Sprague
  • Patent number: 5187793
    Abstract: An instruction caching system comprises meta-instructions which are contained within the program being executed. A meta-machine, which is a small segment of software, executes the meta-instructions and passes control to the processor itself at appropriate times to execute blocks of instructions from the instruction cache.
    Type: Grant
    Filed: January 9, 1989
    Date of Patent: February 16, 1993
    Assignee: Intel Corporation
    Inventors: John M. Keith, Allen H. Simon, David L. Sprague, Douglas F. Dixon, Judith A. Goldstein
  • Patent number: 5148381
    Abstract: An interpolator array having a plurality of interpolator array cells is provided for receiving first and second input values to be interpolated and an interpolator weight term, to provide an interpolated output. A bit of each of the two input values to be interpolated is received by an interpolator array cell and applied to a selecting circuit within a cell of the interpolator array. Additionally, an interpolation weight bit of the interpolation weight term is applied to the selection circuit. The selecting circuit applies either the input bit of the first input value or the input bit of the second input value to an adder within the interpolator cell in accordance with the value of the interpolation weight bit. An interpolator array cell also receives a partial product input and a carry-in input and applies these additional inputs to the adder. The adder provides a partial product output and a carry-out in accordance with the applied inputs.
    Type: Grant
    Filed: February 7, 1991
    Date of Patent: September 15, 1992
    Assignee: Intel Corporation
    Inventor: David L. Sprague
  • Patent number: 5088053
    Abstract: A video signal processing system includes a memory for holding digital data, input and output channel circuitry for reading data from and writing data to the memory and processing circuits for processing data read from the memory to produce data to be written to the memory. Each of the input and output channels produces two types of memory request signals, a normal request signal and an urgent request signal. The normal request signal is produced to gain access to the data in the memory for normal read and wire operations. The urgent request signal is produced to access the memory when the processing circuitry is in a paused state waiting either to obtain data from the input channel or to provide data to the output channel. The normal read and write request signals are handled with substantially equal priority by first scheduling circuitry. The urgent request signals are handled by second scheduling circuits according to a fixed priority scheme.
    Type: Grant
    Filed: November 16, 1987
    Date of Patent: February 11, 1992
    Assignee: Intel Corporation
    Inventors: David L. Sprague, Allen H. Simon, Alfred Kwan