Patents by Inventor David L. Stolfa

David L. Stolfa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method of manufacturing a heterojunction BiCMOS integrated circuit
    Patent number: 6461925
    Abstract: A method of manufacturing a heterojunction BiCMOS IC. (100) includes forming a gate electrode (121, 131), forming a protective layer (901, 902) over the gate electrode, forming a semiconductor layer (1101) over the protective layer, depositing an electrically insulative layer (1102, 1103) over the semiconductor layer, using a mask layer (1104) to define a doped region (225) in the semiconductor layer and to define a hole (1201) in the electrically insulative layer, forming an electrically conductive layer (1301) over the electrically insulative layer, using another mask layer (1302) to define an emitter region (240) in the electrically conductive layer and to define an intrinsic base region (231) and a portion of an extrinsic base region (232) in the electrically conductive layer, and using yet another mask layer (1502) to define another portion of the extrinsic base region in the electrically conductive layer.
    Type: Grant
    Filed: March 30, 2000
    Date of Patent: October 8, 2002
    Assignee: Motorola, Inc.
    Inventors: Jay P. John, James A. Kirchgessner, Ik-Sung Lim, Michael H. Kaneshiro, Vida Ilderem Burger, Phillip W. Dahl, David L. Stolfa, Richard W. Mauntel, John W. Steele
  • High Q integrated resonator structure
    Patent number: 5959515
    Abstract: A high Q integrated inductor-capacitor (L-C) resonator (200) includes a planar inductor (201) having a plurality of turns and a serially connected first and second capacitor (205, 207) that is connected in parallel with the planar inductor (201). The first and second capacitors (205, 207) are positioned within at least one turn of the planar inductor (201) for reducing the parasitic interconnection resistance between the planar inductor (201) and first and second capacitor (205, 207) and also increasing the Q factor of the L-C resonator.
    Type: Grant
    Filed: August 11, 1997
    Date of Patent: September 28, 1999
    Assignee: Motorola, Inc.
    Inventors: Kenneth D. Cornett, Branko Avanic, David L. Stolfa
  • Circuit and method of previewing analog trimming
    Patent number: 5361001
    Abstract: An analog trim circuit enables and disables one or more serially connected passive elements for setting characteristics of the circuit. Each passive element has a transistor across its first and second conduction terminals operating in response to a control signal from a control circuit for enabling and disabling conduction through the associated passive element. The control circuits are responsive to a data signal for providing the control signals that enable and disable the conduction through the passive elements. The data signal allows a preview of the trimming results. The fuse in certain ones of the control circuits are blown to set the control signals to fixed values after removal of the data signal.
    Type: Grant
    Filed: December 3, 1993
    Date of Patent: November 1, 1994
    Assignee: Motorola, Inc.
    Inventor: David L. Stolfa