Abstract: A valve repair devices and systems for repairing a native valve of a patient include a spacer, a plurality of paddles, and a plurality of moveable clasp arms. The plurality of moveable clasp arms are disposed between the plurality of paddles and the spacer. The moveable clasp arms are configured to attach to leaflets of a heart valve.

Abstract: A preamp/driver circuit (18) is disclosed which is operable to interface a Bit Line (14) with a Data Line (20). The Bit Line (14) has a plurality of memory cells associated therewith which are selectable by Word Lines. The preamp/driver (18) decouples the Bit Line (14) from the Data Line (20) and drives Data Line (20) from a separate source. The preamp/driver (18) is comprised of a depletion transistor (22) that has the gate thereof connected to the Bit Line (14) and drives a source follower (26). The source follower (26) drives the Data Line (20) from the supply potential. The system is operable during a restore operation to write back to the Bit Line (14) from the Data Line (20) through a Write transistor (28). The restore operation is effected with a restore amplifier with the Read operation effected through a separate sensing device that converts the voltage on the Data Lines to full logic potentials.

Abstract: Electrolessly deposited metal holograms comprising a polymeric substrate having a holographic relief-patterned surface and a metal reflective layer electrolessly deposited to conform to and reproduce the holographic relief patterned. Light incident to the metal surface is reflected to provide an holographic reproduction of an holographic image inherent in said relief-patterned polymeric substrate.

Abstract: A new ensemble of logic elements organized in an array and a method of forming the same wherein the architecture includes a main field of transistor elements formed on a substrate material. A group of load transistors and an array of logic gates are formed on the substrate and are located within the main field of transistors. At least one routing channel is provided in the main field, and an input/output structure is located on the substrate. A region of flip-flop elements, also located within the main field, may be provided. Preferably, a plurality of such groups, arrays and regions are formed in parallel strips extending across the main field, and a perpendicular bussing channel also extends across the field to divide the main field into component arrays. The logic gates may be configurable structures or dedicated inverters, and a plurality of input/output structures may be employed. The method includes the electrical interconnection of these elements into logic terms to form an integrated circuit.

Abstract: A transistor cell element that may be used alone or in a matrix array in large scale integrated circuits includes a substrate onto which an isolation region is fabricated. Inner and outer charge carrier regions having a high density of first charge carriers is formed in the substrate to define a channel region therebetween. The inner carrier region is adjacent the isolation region so that the channel region extends in a closed loop from said isolation region, around the inner carrier region and back to the isolation region, with the outer carrier region surrounding the isolation and channel regions. The channel region has a low density of second charge carriers, having opposite charge than the first charge carriers, and a gate structure including a conductive band and an insulating layer is formed over the channel region. In one alternate embodiment, additional isolation regions may be provided with these regions interrupting the channel region.

Abstract: An element removal tool for use with transmission lines for fluids (such as natural gas) under pressure which permits replacement of the element, in a specific case the axle box which is coupled between a metering chamber and the indexing mechanism in a gas meter, in a fluid transmission system, without shutting off downstream-customer service, the problem of properly seating the axle box in the undergear which drives it, despite slow rotation of the driving mechanism in the metering chamber, being overcome by dual concentric shafts relatively rotatable and slidable with respect to each other, the inner shaft carrying a socket which engages, firmly, the rotatable indexing shaft of the axle box, the outer shaft carrying a socket which is adapted to firmly engage the flange of the axle box for removal and replacement of the axle box, each shaft having at its end remote from its respective socket, a knob for rotating that shaft, the outer shaft passing through and hermetically engaging a stuffing box, connected

Abstract: To assist in locating an underground or otherwise hidden non-electrically-conducting plastic pipe carrying a fluid such as heating gas a tool is provided which comprises a reel of relatively stiff but flexible locator wire, a hermetically-sealing first bushing through which the locator wire passes and a coupler for engaging a pipe exposed to view but coupled to and communicating for fluid flow with the pipe to be located, such coupler being adapted to receive, in snug fashion, said first bushing and including a packing membrane through which said locator wire passes to further assure no loss of fluid from the pipe being located, said locator terminating at its extremity remote from the reel in a guide member having a shape which may be described as suggestive of an oblate spheroid; i.e.

Abstract: A nonvolatile static random access memory cell (10) includes a pair of cross-coupled transistors (12, 14) which function as a bistable circuit to store data states. Variable threshold transistors (36, 41) are respectively connected in series between the driver transistors (12, 14) and load devices (48, 50). A control node (40) is driven to a high voltage state to cause one of the variable threshold transistors (36, 41) to be driven to have a higher threshold voltage and thereby store the data state held in the cross-coupled transistors (12, 14). The data state is thus stored in nonvolatile form. Upon recall the memory cell (10) is reactivated and the threshold differential between the variable threshold transistors (36, 41) causes the driver transistors (12, 14) to be set at the stored data state. The data recalled by the memory cell (10) is in true rather than in complementary form. The variable threshold transistors (36, 41) are reset by driving the power terminal V.sub.

Abstract: In a memory array wherein each cell includes an emitter follower, a diode is formed on the emitter by a thin layer which is capable of being shorted by vertical migration of bit line atoms through the layer and into the emitter region. The thin layer is fabricated by epitaxially growing the thin layer over the wafer with the emitter diffusion aperture open, oxidizing the epitaxial layer, selectively removing portions of the polycrystalline epitaxial layer and removing the oxide from the remaining epitaxial layer in the emitter diffusion aperture.

Abstract: An integrated circuit memory including a random memory (RAM) and a plurality of electrically alterable read only memories (EAROMS) having common controls. The data input for the RAM is either the system input or an EAROM and the data input for the EAROMS is only from the RAM. The system data output is from the RAM and the EAROMS.

Abstract: An improved linear to digital translator having parallel current paths with unequal resistances. The resistances are sized according to a determined relationship between circuit parameters to improve crossover performance. In addition, non-saturating devices are used to reduce delay times.

Abstract: A bipolar device is formed in an N epitaxial layer region isolated from an N substrate and the remainder of the N epitaxial layer by a P surface ring and a buried P region. An N channel device is formed in the P surface ring and a P channel device is formed in the N epitaxial layer. A buried N region is formed in the buried P region using the same mask used to form the buried P region.

Abstract: In a memory array wherein each cell includes an emitter follower, a diode is formed on the emitter by a thin layer which is capable of being shorted by vertical migration of bit line atoms through the layer and into the emitter region. The thin layer is fabricated by epitaxially growing the thin layer over the wafer with the emitter diffusion aperture open, oxidizing the epitaxial layer, selectively removing portions of the polycrystalline epitaxial layer and removing the oxide from the remaining epitaxial layer in the emitter diffusion aperture.

Abstract: A buffer having a first and second complementary IGFET input inverter connected in series and an output including a bipolar emitter follower with its base connected to the output of the first inverter, a second bipolar transistor connected in series with the emitter follower with its base connected to the output of the second inverter and an IGFET connected between the junction of the bipolar transistors and a voltage supply terminal and with its gate connected to the input of the first inverter. The output IGFET pulls the buffer output up to the supply voltage when the emitter of the emitter follower is at the supply voltage minus V.sub.BE.

Abstract: Block redundancy is utilized to improve yield and lower die cost for an electrically programmable read only memory (EPROM). The EPROM is organized 8Kx8 with four primary memory blocks on each side of a central row decoder. Each block includes an array of memory cells, column select, column decode, sense amp, data buffer and other overhead circuitry. One block of redundant circuitry is also provided for each set of four blocks and includes a redundant memory matrix, a redundant column decoder, a redundant column select, a redundant sense amp and a redundant data buffer. Incorporated within each primary memory block is a multiplex logic circuit which is independently programmable to selectively disconnect the associated primary memory block and substitute the redundant memory block, including the redundant column decoder, column select, sense amp and data buffer.

Abstract: A memory array wherein each memory cell includes a resistive device which switches from a high to a low resistance state when a potential above its programmable threshold is applied and including a reference cell per word line having a reference switchable resistive device. Using a ramp addressing potential, the array output is disabled by an output disable circuit after a reference resistive device switches which is after the switching of an addressed low threshold resistive device cell and before the switching of an addressed high threshold resistive device cell.

Abstract: A RAM cell having a pair of transistors formed in two adjacent wells laterally separated from each other and surrounded laterally by a common doped polycrystalline semiconductor moat. Dielectrical insulation separate the wells from the moat. The moat is discontinuous, forming thereby a pair of resistors connected together at one end and disconnected at the discontinuity. Surface contacts bridge adjacent areas of the well and the moat which are of the same conductivity type whereby the moat forms the load resistor for the transistor. Each transistor includes a second emitter.First level interconnects include a first interconnect interconnecting an emitter from each transistor, a second interconnect parallel to the first contacting the connected end of the moat resistors, a pair of interconnects each interconnecting the bridge contact of one transistor to the base of the other, and a pair of contacts for the other emitter regions.

Abstract: A memory array wherein each memory cell includes a pair of threshold resistive elements which switch from a high to a low resistance state when a potential above their respective programmable thresholds is applied. A binary value is stored by creating a threshold difference between the two resistive elements using two different value current sources. The binary value stored is read by applying a ramp potential and determining which threshold resistive element switched states first using a sense latch.

Abstract: A RAM cell having a pair of transistors formed in two adjacent wells laterally separated from each other and surrounded laterally by a common doped polycrystalline semiconductor moat. Dielectrical insulation separate the wells from the moat. The moat is discontinuous, forming thereby a pair of resistors connected together at one end and disconnected at the discontinuity. Surface contacts bridge adjacent areas of the well and the moat which are of the same conductivity type whereby the moat forms the load resistor for the transistor. Each transistor includes a second emitter.First level interconnects include a first interconnect interconnecting an emitter from each transistor, a second interconnect parallel to the first contacting the connected end of the moat resistors, a pair of interconnects each interconnecting the bridge contact of one transistor to the base of the other, and a pair of contacts for the other emitter regions.

Abstract: A field effect transistor amplifier for use as on the output buffer for semiconductor memories including an electrically alterable element added to an active pull up configuration to allow conversion between active pull up and open drain nonvolatile configurations reversibly or irreversibly. A fusible element or P-N junction device is electrically alterable for irreversible configuration conversion and an amorphous material element is electrically alterable for reversible and irreversible configuration conversion.