Abstract: An apparatus for performing exercises including a case for transporting the exercise device and for use in performing the exercises. The case can be a simulated briefcase, so that the exercise device can be carried around like ordinary luggage, or be another type of container. Included are elastic cables which can be moved from stowed positions in the case to exercising positions in which portions of the cables extend outwardly from the case. The portions of the cables remaining in the case are restrained against stretching thereby allowing essentially only the portions of the cables extending outwardly from the case to be stretched. In performing exercises, the outwardly extending portions of the cables are pulled against the case, thereby setting up isometric forces which resist the pulling action and enable the desired strength training. It is possible to exercise all of the major muscle groups and to replicate the exercises performed on popular stationary exercise apparatus.

Abstract: A telephone instrument with a 12-key keypad that has relegendable buttons. The telephone instrument is coupled to apparatus such as a personal computer, network server, or switch that is capable of performing telephony functions. The telephony apparatus responds to an input from the keypad by providing a new set of legends for the keys and/or performing a telephone function. In a preferred embodiment, the telephone instrument is connected both to a personal computer and to a POTS telephone circuit and includes a separate keypad for the POTS telephone circuit. The apparatus includes a component which detects a failure in the personal computer and automatically deactivates the keypad with the relegendable buttons, leaving the telephone instrument still available for use with the POTS circuit.

Abstract: An apparatus for performing exercises including a case for transporting the exercise device and for use in performing the exercises. The case can be a simulated briefcase, so that the exercise device can be carried around like ordinary luggage, or be another type of container. Included are elastic cables which can be moved from stowed positions in the case to exercising positions in which portions of the cables extend outwardly from the case. The portions of the cables remaining in the case are restrained against stretching thereby allowing essentially only the portions of the cables extending outwardly from the case to be stretched. In performing exercises, the outwardly extending portions of the cables are pulled against the case, thereby setting up forces which resist the pulling action and enable the desired strength training. It is possible to exercise all of the major muscle groups and to replicate the exercises performed on popular stationary exercise apparatus.

Abstract: Telephone station equipment consisting of a phone device interconnected with a personal computer. The phone device includes a conventional telephone handset and a keypad employing pushbutton display keys each of which has a writable keyface display for visually indicating the function of the key or other information to the user. The personal computer is connected to both the phone device and to one or more telephone communications channels and is programmed to display prompting information on the key displays and respond to keypress events to perform the functions indicated. The user can perform a variety of telephone system management tasks solely by viewing and manipulating the phone device keypad, including manual dialing, redialing, speed-dialing from a directory of commonly called numbers, making flash disconnections, forwaring calls, controlling call waiting and caller I.D.

Abstract: An I/O structure for use in a digital data processing system of the type in which system components including a processor and a system memory are connected by a system bus. The I/O structure includes a system bus interface connected to the system bus, a synchronous satellite processing unit (SPU) bus connected to the system bus interface, one or more satellite processing units (SPUs) connected to the SPU bus, and peripheral devices attached to the satellite processing units. Each SPU has three main components: control logic including a microprocessor for controlling the SPU, a device adapter specific to the peripheral device for controlling the peripheral device and transferring data between the peripheral device and the SPU, and an interface unit connected to the control logic and the device adapter for providing I/O communications to the SPU bus and responding to I/O communications on the SPU bus. The I/O communications fall into two classes: communications to SPUs and communications to system components.

Abstract: Apparatus for determining priority of access to a bus by nodes in a group of nodes attached to the bus. For purposes of determining priority, the apparatus arranges the nodes in a circular configuration and selects one of the nodes as the "anchor node". The anchor node has the highest priority and the priorities of the other nodes are determined by their positions in the circle relative to the anchor node. Each node includes a presettable counter for indicating a number of times that a node may access the bus before the highest priority is rotated to another node. After a device represented by one of the nodes accesses the bus for a predetermined number of accesses the current anchor node ceases being the anchor node and the next node in the circle becomes the new anchor node. The priorities of the nodes change to reflect the new location of the anchor node.

Abstract: Apparatus for determining priority of access to a bus by nodes in a group of nodes attached to the bus. For purposes of determining priority, the apparatus arranges the nodes in a circular configuration and selects one of the nodes as the "anchor node". The anchor node has the highest priority and the priorities of the other nodes are determined by their positions in the circle relative to the anchor node. Each time a device represented by one of the nodes accesses the bus, the current anchor node ceases being the anchor node and the next node in the circle becomes the new anchor node. The priorities of the nodes change to reflect the new location of the anchor node.

Abstract: A system bus and bus interface apparatus for connecting components in a data processing system having a plurality of non-memory and memory components. The system bus has the following sets of lines; A first plurality of lines carries a plurality of codes specifying a plurality of memory operations involving communications between a non-memory component and a memory component and a single code specifying an interprocessor communication between two non-memory components. A second plurality of lines carries an address in a memory component when the code on the first plurality of lines specifies a memory operation and a target address, an interprocessor communication type, and in some cases, a message, when the code on the first plurality of lines specifies an interprocessor communication.

Abstract: A memory system connected by means of a system bus to other components of a data processing system. The memory system includes a memory control unit and at least one memory unit in which information units containing two words are stored. The memory control unit is connected to the system bus and receives system addresses and memory commands from the system bus, and depending on the memory command, receives data from or provides data to the system bus. A memory bus and lines for control signals specifying memory requests connect the memory control unit and the memory unit. The memory bus is time multiplexed between memory addresses and information units. The memory control unit receives a memory command, a system address, and in the case of a write command, system data on the system bus and produces the memory requests, memory addresses, and information units required to carry out the memory command.

Abstract: A memory device is disclosed that operates internally substantially independent of the timing of signals from its associated computer. That is, the timing controls for multiplexing the row and column address into the memory chips as well as the enabling signal for writing information into the chips are controlled by different delay lines so that the memory always operates at its optimal operational speed. In addition, the input and output latches are arranged to receive or output information to or from the computer at a time that is optimal for the computer or other information requester.

Abstract: A Floating Point Processor or Floating Point Unit (FPU) with capability for performing exponent/sign-related calculations concurrently with mantissa-related calculations. The operation of the FPU within the context of a general purpose digital computer system is shown. The FPU has control, mantissa, and exponent/sign functional blocks which have unique architectural arrangements and interconnections therebetween, and also have interfacing structure for connecting system control and clock signals to the control block. The operation of the FPU is timed in a particular manner to permit its operation to be transparent to, or to not impact operation of the CPU, when the FPU communicates with main memory or the CPU.