Abstract: An integrated circuit digital device, acting as a master, communicates with at least one peripheral device, acting as a slave, using an enhanced single-node protocol for data, address and control operation. The peripheral device may be selected from any number of different functions. The peripheral device may be packaged in a low pin count integrated circuit package. At a minimum, the peripheral device integrated circuit package may have a ground terminal, VSS; a power terminal, VDD or VCC; and a bidirectional serial clock, and data and control input-output (SCIO) terminal. Acknowledgment sequences from both the master and slave devices ensure robust communications therebetween.

Abstract: An integrated circuit digital device, acting as a master, communicates with at least one peripheral device, acting as a slave, using an enhanced single-node protocol for data, address and control operation. The peripheral device may be selected from any number of different functions. The peripheral device may be packaged in a low pin count integrated circuit package. At a minimum, the peripheral device integrated circuit package may have a ground terminal, VSS; a power terminal, VDD or VCC; and a bidirectional serial clock, and data and control input-output (SCIO) terminal. Acknowledgment sequences from both the master and slave devices ensure robust communications therebetween.

Abstract: A sacrificial lead and a common lead hold a die paddle of each integrated circuit SOT-23 package to a leadframe within a strip of leadframes after isolating signal leads from the leadframe. Strip testing of most devices in the SOT-23 three and five lead packages may then be performed. The common lead may be at the center of an edge of the SOT-23 package. Also the common lead may be any one of the leads of the SOT-23 package. In addition the sacrificial lead may be at the center of an opposite edge of the SOT-23 package.

Abstract: An integrated circuit digital device is coupled to a memory with a single-node data, address and control bus. The memory may be a non-volatile memory and/or volatile memory. The memory may be packaged in a low pin count integrated circuit package. The memory integrated circuit package may have a ground terminal, VSS; a power terminal, VDD or VCC; and a bidirectional serial input-output (I/O) terminal, SCIO. Memory block address set-up may be performed via software instructions through the SCIO terminal. In addition, hardwired memory block address selection terminals A0 and A1 may be used when more then three terminals are available on the memory integrated circuit package. The memory may have active pull-up and pull-down drivers coupled to the single-node data, address and control bus.