Patents by Inventor David Laforet

David Laforet has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180175150
    Abstract: A body structure and a drift zone are formed in a semiconductor layer, wherein the body structure and the drift zone form a first pn junction. A silicon nitride layer is formed on the semiconductor layer. A silicon oxide layer is formed from at least a vertical section of the silicon nitride layer by oxygen radical oxidation.
    Type: Application
    Filed: December 20, 2017
    Publication date: June 21, 2018
    Applicant: Infineon Technologies AG
    Inventors: Anton MAUDER, Oliver HELLMUND, Peter IRSIGLER, Jens Peter KONRATH, David LAFORET, Maik LANGNER, Markus NEUBER, Hans-Joachim SCHULZE, Ralf SIEMIENIEC, Knut STAHRENBERG, Olaf STORBECK
  • Patent number: 9972714
    Abstract: A semiconductor device includes a cell field with a plurality of field electrode structures and cell mesas. The field electrode structures are arranged in lines. The cell mesas separate neighboring ones of the field electrode structures from each other. Each field electrode structure includes a field electrode and a field dielectric separating the field electrode from a semiconductor body. A termination structure surrounds the cell field, extends from a first surface into the semiconductor body, and includes a termination electrode and a termination dielectric separating the termination electrode from the semiconductor body. The termination and field dielectrics have the same thickness. A termination mesa, which is wider than the cell mesas, separates the termination structure from the cell field.
    Type: Grant
    Filed: August 27, 2015
    Date of Patent: May 15, 2018
    Assignee: INFINEON TECHNOLOGIES AUSTRIA AG
    Inventors: David LaForet, Ralf Siemieniec
  • Publication number: 20180122934
    Abstract: A semiconductor device includes a gate structure extending from a first surface into a semiconductor portion and having a metal gate electrode and a gate dielectric separating the metal gate electrode from the semiconductor portion. An interlayer dielectric separates a first load electrode from the semiconductor portion, and includes a screen oxide layer thinner than the gate dielectric. A body zone and a source zone are formed in the semiconductor portion and directly adjoin the gate structure.
    Type: Application
    Filed: December 27, 2017
    Publication date: May 3, 2018
    Inventors: David Laforet, Cedric Ouvrard
  • Patent number: 9865726
    Abstract: A screen oxide layer is formed on a main surface of a semiconductor layer and a passivation layer is formed on the screen oxide layer. A gate trench is formed in a portion of the semiconductor layer exposed by a mask opening in a trench mask that comprises the passivation layer. A gate dielectric is formed at least along sidewalls of the gate trench. After removing the passivation layer, dopants are implanted through the screen oxide layer to form at least one of a source zone and a body zone in the semiconductor layer.
    Type: Grant
    Filed: October 13, 2016
    Date of Patent: January 9, 2018
    Assignee: Infineon Technologies Austria AG
    Inventors: David Laforet, Cedric Ouvrard
  • Patent number: 9847395
    Abstract: A semiconductor device includes a gate structure that extends from a first surface into a semiconductor portion and that surrounds a transistor section of the semiconductor portion. A field plate structure includes a field electrode and extends from the first surface into the transistor section. A mesa section of the semiconductor portion separates the field plate structure and the gate structure. A contact structure includes a first portion directly adjoining the mesa section and a second portion directly adjoining the field electrode. The first and second portions include stripes and are directly connected to each other.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: December 19, 2017
    Assignee: Infineon Technologies Austria AG
    Inventors: David Laforet, Elisabeth Schwarz, Beate Weissnicht
  • Publication number: 20170345924
    Abstract: In one implementation, a reduced gate charge field-effect transistor (FET) includes a drift region situated over a drain, a body situated over the drift region, and source diffusions formed in the body. The source diffusions are adjacent a gate trench extending through the body into the drift region and having a dielectric liner and a gate electrode situated therein. The dielectric liner includes an upper segment and a lower segment, the upper segment extending to at least a depth of the source diffusions and being significantly thicker than the lower segment.
    Type: Application
    Filed: August 17, 2017
    Publication date: November 30, 2017
    Inventors: David Laforet, Li Juin Yip, Cedric Ouvrard
  • Patent number: 9799738
    Abstract: A semiconductor device includes a field electrode structure with a field electrode and a field dielectric surrounding the field electrode. A semiconductor body includes a transistor section surrounding the field electrode structure and including a source zone, a first drift zone section and a body zone separating the source zone and the first drift zone section. The body zone forms a first pn junction with the source zone and a second pn junction with the first drift zone section. A gate structure surrounds the field electrode structure and includes a gate electrode and a gate dielectric separating the gate electrode and the body zone. A contact structure directly adjoins the source and body zones and surrounds the field electrode structure equably with respect to the field electrode structure.
    Type: Grant
    Filed: August 7, 2015
    Date of Patent: October 24, 2017
    Assignee: Infineon Technologies Austria AG
    Inventors: Ralf Siemieniec, Oliver Blank, Michael Hutzler, David Laforet, Cedric Ouvrard, Li Juin Yip
  • Publication number: 20170271491
    Abstract: A vertical semiconductor field-effect transistor includes a semiconductor body having a front side, and a field electrode trench extending from the front side into the semiconductor body The field electrode trench includes a field electrode and a field dielectric arranged between the field electrode and the semiconductor body. The vertical semiconductor field-effect transistor further includes a gate electrode trench arranged next to the field electrode trench, extending from the front side into the semiconductor body, and having two electrodes which are separated from each other and the semiconductor body. A front side metallization is arranged on the front side and in contact with the field electrode and at most one of the two electrodes.
    Type: Application
    Filed: March 14, 2017
    Publication date: September 21, 2017
    Inventors: Li Juin Yip, Cesar Augusto Braz, Olivier Guillemant, David Laforet, Cedric Ouvrard
  • Patent number: 9755066
    Abstract: In one implementation, a reduced gate charge field-effect transistor (FET) includes a drift region situated over a drain, a body situated over the drift region, and source diffusions formed in the body. The source diffusions are adjacent a gate trench extending through the body into the drift region and having a dielectric liner and a gate electrode situated therein. The dielectric liner includes an upper segment and a lower segment, the upper segment extending to at least a depth of the source diffusions and being significantly thicker than the lower segment.
    Type: Grant
    Filed: November 30, 2015
    Date of Patent: September 5, 2017
    Assignee: Infineon Technologies Austria AG
    Inventors: David Laforet, Li Juin Yip, Cedric Ouvrard
  • Publication number: 20170250255
    Abstract: A semiconductor device includes a semiconductor substrate, a transistor cell region formed in the semiconductor substrate and an inner termination region formed in the semiconductor substrate and devoid of transistor cells. The transistor cell region includes a plurality of transistor cells and a gate structure that forms a grid separating transistor sections of the transistor cells from each other, each of the transistor sections including a needle-shaped first field plate structure extending from a first surface into the semiconductor substrate. The inner termination region surrounds the transistor cell region and includes needle-shaped second field plate structures extending from the first surface into the semiconductor substrate. The first field plate structures form a first portion of a regular pattern and the second field plate structures form a second portion of the same regular pattern.
    Type: Application
    Filed: February 20, 2017
    Publication date: August 31, 2017
    Inventors: Ralf Siemieniec, Oliver Blank, Franz Hirler, Michael Hutzler, David Laforet, Cedric Ouvrard, Li Juin Yip
  • Publication number: 20170250256
    Abstract: A semiconductor device includes needle-shaped field plate structures extending from a first surface into transistor sections of a semiconductor portion in a transistor cell area. A grid structure separates the transistor sections from each other. The grid structure includes: stripe-shaped gate edge portions extending along one edge of the transistor sections, respectively; gate node portions wider than the gate edge portions and connecting two or more of the gate edge portions, respectively; and one or more connection sections of the semiconductor portion, wherein the one or more connection sections extend between neighboring transistor sections.
    Type: Application
    Filed: February 23, 2017
    Publication date: August 31, 2017
    Inventors: Ralf Siemieniec, Oliver Blank, David Laforet, Cedric Ouvrard, Li Juin Yip
  • Publication number: 20170236910
    Abstract: A method of manufacturing a power metal oxide semiconductor field effect transistor includes: forming a field electrode in a field plate trench in a main surface of a semiconductor substrate; forming a gate trench in the main surface, the gate trench extending in a first direction parallel to the main surface; and for a gate electrode in the gate trench, the gate electrode being made of a gate electrode material that comprises a metal. The field plate trench is formed to have an extension length in the first direction which is less than double of an extension length of the field plate trench in a second direction, the second direction being perpendicular to the first direction.
    Type: Application
    Filed: May 2, 2017
    Publication date: August 17, 2017
    Inventors: David Laforet, Oliver Blank, Michael Hutzler, Cedric Ouvrard, Ralf Siemieniec, Li Juin Yip
  • Patent number: 9728614
    Abstract: A semiconductor device is manufactured by forming a gate electrode adjacent to a body region in a semiconductor substrate, forming a field plate trench in a main surface of the substrate, the field plate trench having an extension length in a first direction parallel to the main surface, and forming a field electrode and a field dielectric layer in the field plate trench so that the field electrode is insulated from an adjacent drift zone by the field dielectric layer. The extension length of the field plate trench in the first direction is less than double an extension length of the field electrode in a second direction that is perpendicular to the first direction and is parallel to the main surface. The extension length in the first direction is more than half the extension length in the second direction.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: August 8, 2017
    Assignee: Infineon Technologies Austria AG
    Inventors: David Laforet, Oliver Blank, Franz Hirler, Ralf Siemieniec
  • Patent number: 9680004
    Abstract: A power MOSFET includes a gate electrode in a gate trench in a main surface of a semiconductor substrate, the gate trench extending parallel to the main surface. The power MOSFET further includes a field electrode in a field plate trench in the main surface. The field plate trench has an extension length in a first direction which is less than double and more than half of an extension length of the field plate trench in a second direction perpendicular to the first direction, the first and the second directions being parallel to the main surface. The gate electrode includes a gate electrode material which comprises a metal.
    Type: Grant
    Filed: July 8, 2015
    Date of Patent: June 13, 2017
    Assignee: Infineon Technologies Austria AG
    Inventors: David Laforet, Oliver Blank, Michael Hutzler, Cedric Ouvrard, Ralf Siemieniec, Li Juin Yip
  • Publication number: 20170154993
    Abstract: In one implementation, a reduced gate charge field-effect transistor (FET) includes a drift region situated over a drain, a body situated over the drift region, and source diffusions formed in the body. The source diffusions are adjacent a gate trench extending through the body into the drift region and having a dielectric liner and a gate electrode situated therein. The dielectric liner includes an upper segment and a lower segment, the upper segment extending to at least a depth of the source diffusions and being significantly thicker than the lower segment.
    Type: Application
    Filed: November 30, 2015
    Publication date: June 1, 2017
    Inventors: David Laforet, Li Juin Yip, Cedric Ouvrard
  • Publication number: 20170110573
    Abstract: A screen oxide layer is formed on a main surface of a semiconductor layer and a passivation layer is formed on the screen oxide layer. A gate trench is formed in a portion of the semiconductor layer exposed by a mask opening in a trench mask that comprises the passivation layer. A gate dielectric is formed at least along sidewalls of the gate trench. After removing the passivation layer, dopants are implanted through the screen oxide layer to form at least one of a source zone and a body zone in the semiconductor layer.
    Type: Application
    Filed: October 13, 2016
    Publication date: April 20, 2017
    Inventors: David Laforet, Cedric Ouvrard
  • Publication number: 20170104078
    Abstract: A semiconductor device is manufactured by forming a gate electrode adjacent to a body region in a semiconductor substrate, forming a field plate trench in a main surface of the substrate, the field plate trench having an extension length in a first direction parallel to the main surface, and forming a field electrode and a field dielectric layer in the field plate trench so that the field electrode is insulated from an adjacent drift zone by the field dielectric layer. The extension length of the field plate trench in the first direction is less than double an extension length of the field electrode in a second direction that is perpendicular to the first direction and is parallel to the main surface. The extension length in the first direction is more than half the extension length in the second direction.
    Type: Application
    Filed: December 22, 2016
    Publication date: April 13, 2017
    Inventors: David Laforet, Oliver Blank, Franz Hirler, Ralf Siemieniec
  • Patent number: 9621058
    Abstract: A synchronous rectifier is described that includes a transistor device that has a gate terminal, a source terminal, a drain terminal, and a field-plate electrode. The field-plate electrode of the transistor device includes an integrated diode. The integrated diode is configured to discharge a parasitic capacitance of the transistor device during each switching operation of the synchronous rectifier. In some examples, the integrated diode is also configured to charge the parasitic capacitance of the transistor device during each switching operation of the synchronous rectifier.
    Type: Grant
    Filed: January 20, 2015
    Date of Patent: April 11, 2017
    Assignee: Infineon Technologies Austria AG
    Inventors: Cesar Augusto Braz, David Laforet
  • Publication number: 20170077227
    Abstract: There are disclosed herein various implementations of a vertical metal-oxide-semiconductor field-effect transistor (MOSFET). Such a vertical MOSFET includes a semiconductor substrate having a drift region situated over a drain, a gate trench and needle field plates extending into the drift region, and source regions situated in respective mesas. In addition, the vertical MOSFET includes mesa contacts having a first width and extending through a first pre-metal dielectric layer to make electrical contact with the mesas. A second pre-metal dielectric layer is situated over the first pre-metal dielectric layer and the mesa contacts. The vertical MOSFET further includes conductive posts having a second width less than the first width and extending through the second pre-metal dielectric layer to make electrical contact with the mesa contacts.
    Type: Application
    Filed: September 11, 2015
    Publication date: March 16, 2017
    Inventors: David Laforet, Li Juin Yip, Cedric Ouvrard
  • Publication number: 20170005171
    Abstract: A semiconductor device includes a gate structure that extends from a first surface into a semiconductor portion and that surrounds a transistor section of the semiconductor portion. A field plate structure includes a field electrode and extends from the first surface into the transistor section. A mesa section of the semiconductor portion separates the field plate structure and the gate structure. A contact structure includes a first portion directly adjoining the mesa section and a second portion directly adjoining the field electrode. The first and second portions include stripes and are directly connected to each other.
    Type: Application
    Filed: July 1, 2016
    Publication date: January 5, 2017
    Inventors: David Laforet, Elisabeth Schwarz, Beate Weissnicht