Abstract: A device for reducing communications crosstalk including a plurality of channel inputs each configured to receive an incoming signal from a respective device. The device further includes at least one control input configured such that, when the control input is triggered, the control input activates a voltage divider that attenuates at least one of the incoming signals, thereby reducing crosstalk between a first channel carrying the at least one attenuated incoming signal and a second channel not carrying the at least one attenuated incoming signal. The at least one attenuated incoming signal and the remaining incoming signals are output to a respective receiver.

Abstract: A device for reducing communications crosstalk including a plurality of channel inputs each configured to receive an incoming signal from a respective device. The device further includes at least one control input configured such that, when the control input is triggered, the control input activates a voltage divider that attenuates at least one of the incoming signals, thereby reducing crosstalk between a first channel carrying the at least one attenuated incoming signal and a second channel not carrying the at least one attenuated incoming signal. The at least one attenuated incoming signal and the remaining incoming signals are output to a respective receiver.

Abstract: A device for reducing communications crosstalk including a plurality of channel inputs each configured to receive an incoming signal from a respective device. The device further includes at least one control input configured such that, when the control input is triggered, the control input activates a voltage divider that attenuates at least one of the incoming signals, thereby reducing crosstalk between a first channel carrying the at least one attenuated incoming signal and a second channel not carrying the at least one attenuated incoming signal. The at least one attenuated incoming signal and the remaining incoming signals are output to a respective receiver.

Abstract: A device for reducing communications crosstalk including a plurality of channel inputs each configured to receive an incoming signal from a respective device. The device further includes at least one control input configured such that, when the control input is triggered, the control input activates a voltage divider that attenuates at least one of the incoming signals, thereby reducing crosstalk between a first channel carrying the at least one attenuated incoming signal and a second channel not carrying the at least one attenuated incoming signal. The at least one attenuated incoming signal and the remaining incoming signals are output to a respective receiver.

Abstract: An apparatus for OFDM communications includes an equalizer filter configured to receive input data and to apply a tap setting to the input data to generate output data. The input data includes a first real component and a first imaginary component. The tap setting includes a second real component and a second imaginary component. The output data includes a third real component and a third imaginary component, and the third real component is time-multiplexed with the third imaginary component. A method for OFDM communications includes applying a tap setting to input data to generate output data.

Abstract: An audio/video system (100) is capable of introducing variable amounts of delay into a signal path so as to properly synchronize two signals, such a video signal and a corresponding audio signal. According to an exemplary embodiment, the audio/video system (100) includes first circuitry (50) for applying a first delay to a first digital signal. Second circuitry (80) applies a variable second delay to a second digital signal to time align the second digital signal relative to the first digital signal. The second circuitry (80) includes an addressable memory (84) for selectively storing the second digital signal and for outputting the second digital signal on a first-in, first-out basis to apply the variable second delay to the second digital signal.

Abstract: An integrated circuit (IC) includes an internal clock generator apparatus that provides various modes of operation of the integrated circuit. The internal clock generator apparatus includes a clock generator portion that is operable to provide a clock signal for various circuitry/logic of the integrated circuit and a control portion that is operable to receive a control signal to cause the integrated circuit to operate in one of several modes. In particular, the clock generator apparatus is responsive to the control signal, preferably from an external source, to bypass the clock signal, introduce a test clock signal for digital testing, and isolate and/or measure a delay through the clock generator portion of the clock generator apparatus.

Abstract: A multiple clock IC has a single, bi-directional clock I/O pin for each internally generated clock signal, with the functionality of each bi-directional clock I/O pin controllable to allow various modes of operation. Mode control of the clock I/O pins and associated circuitry/logic is preferably achieved via control signals supplied to I2C registers via an I2C bus/protocol system. The present invention allows for a normal mode of operation of the clocks, a debugging mode of operation for observation of the internal IC clocks, and/or a test mode of operation to drive the internal IC clock from the pin through the respective bi-directional I/O pin. The present invention is useful for both digital testing of the IC (when precise control over the test clock phase and timing is important) and for debugging. All of the modes of the IC clock signals are independently controllable.

Abstract: An audio/video system (100) is capable of introducing variable amounts of delay into a signal path so as to properly synchronize two signals, such a video signal and a corresponding audio signal. According to an exemplary embodiment, the audio/video system (100) includes first circuitry (50) for applying a first delay to a first digital signal. Second circuitry (80) applies a variable second delay to a second digital signal to time align the second digital signal relative to the first digital signal. The second circuitry (80) includes an addressable memory (84) for selectively storing the second digital signal and for outputting the second digital signal on a first-in, first-out basis to apply the variable second delay to the second digital signal.

Abstract: Interface apparatus for interfacing data to a plurality of different clock domains where the clock signals in the different domains are phase locked together and respective clock signals have different frequencies includes a plurality of cascade connected first and second latches coupled between respective clock domains. One of the latches is a clocked Data Latch and the other is a clocked and Enabled Data Latch. A timing generator provides respective domain clock signals, wherein a domain clock signal of a domain providing a data signal is applied to the clock input connection of the first latch of a respective cascade connected set of latches and a domain clock signal of a domain receiving said data signal is applied to the second latch. The timing generator also provides a common Enable Signal phase locked to the domain clocked signals. The common Enable Signal is applied to the enable input terminal of one of the latches of each set of cascade connected latches.

Abstract: An integrated circuit (IC) includes an internal clock generator apparatus that provides various modes of operation of the integrated circuit. The internal clock generator apparatus includes a clock generator portion that is operable to provide a clock signal for various circuitry/logic of the integrated circuit and a control portion that is operable to receive a control signal to cause the integrated circuit to operate in one of several modes. In particular, the clock generator apparatus is responsive to the control signal, preferably from an external source, to bypass the clock signal, introduce a test clock signal for digital testing, and isolate and/or measure a delay through the clock generator portion of the clock generator apparatus.

Abstract: A digital frequency multiplier provides non-integer frequency multiplication of an input signal. A multiplexer receives the input signal and an integer multiple of the input signal. A multiplexer control signal selects/toggles which signal the multiplexer will output and how long. A counter, clocked by one of the signals, provides the multiplexer control signal. The multiplexer outputs a pre-determined number of clock cycles of each signal to produce the desired non-integer frequency multiplied input signal. The present invention generates frequency multiplication without a phase locked loop (PLL).

Abstract: A system and method is described for providing a single pin reset for a mixed signal integrated circuit. The system and method provides for a single reset signal/pin of the integrated circuit to be utilized to generate all internal resets for the analog and digital circuitry/sections of the mixed signal integrated circuit. In one form, a state machine generates a reset signal for a phase locked loop synthesizer that is utilized to generate internal system clocks for the analog and digital circuitry, as well as a digital reset signal that provides reset signals to the various digital sections circuitry of the integrated circuit. Preferably, the chip reset signal is provided for a longer period of time than the PLL reset signal in order to assure that the PLL is running and generating clocking signals before the digital logic is clocked.

Abstract: A digital frequency multiplier provides non-integer frequency multiplication of an input signal. A multiplexer receives the input signal and an integer multiple of the input signal. A multiplexer control signal selects/toggles which signal the multiplexer will output and how long. A counter, clocked by one of the signals, provides the multiplexer control signal. The multiplexer outputs a pre-determined number of clock cycles of each signal to produce the desired non-integer frequency multiplied input signal. The present invention generates frequency multiplication without a phase locked loop (PLL).

Abstract: Analog to digital converters with enhanced performance in the presence of clock noise interference are configured with sampling clock phase selection circuitry to enable operation of the converter at the optimum sampling time intervals with respect to the interfering noise. The selection circuitry includes apparatus for generating a plurality of sampling clock phases and a multiplexer coupled to the plurality of phases to select the optimum clock phase.

Abstract: An expander circuit for decoding audio signals which were encoded in accordance with the BTSC multichannel sound system standard including DBX commanding is presented. A wideband expander circuit is utilized and a DBX expander can be accommodated. The wideband expander circuit is provided with a signal path having an input LPF (low pass filter), a stereo difference signal (L?R) demodulator, a second LPF, and a voltage controlled amplifier (VCA), the gain of which is controlled by a control signal derived from the demodulated difference signal which has been operated on by a bandpass filter (BPF) and an integrating peak detector. The output of the VCA is provided to a deemphasis network before being fed to a decoder matrix for combining with the sum stereo signal (L+R) for reconstructing the original L and R signals.