Abstract: A package includes a bridging element (an OMIB), and first and second photonic paths, forming a bidirectional photonic path. The OMIB has first and second interconnect regions to connect with one or more dies. Third and fourth unidirectional photonic paths may couple between the first interconnect region and an optical interface (OI). A photonic transceiver has a first portion in the OMIB and a second portion in one of the dies. The first and the second portions may be coupled via an electrical interconnect less than 2 mm in length. The die includes compute elements around a central region, proximate to the second portion. The OMIB may include an electro-absorption modulator fabricated with germanium, silicon, an alloy of germanium, an alloy of silicon, a III-V material based on indium phosphide (InP), or a III-V material based on gallium arsenide (GaAs). The OMIB may include a temperature compensation for the modulator.

Abstract: Disclosed here are systems, methods, and apparatuses for single-ended electro-absorption modulators (EAMs) with electrical combining. In particular, systems and methods are disclosed for performing optical encoding and multiplication operation for optical signal without applying a sign value. The optical output can be converted into a photocurrent input and the sign value can be applied to the photocurrent input on an electrical layer.

Abstract: A package includes a bridging element (an OMIB), and first and second photonic paths, forming a bidirectional photonic path. The OMIB has first and second interconnect regions to connect with one or more dies. Third and fourth unidirectional photonic paths may couple between the first interconnect region and an optical interface (OI). A photonic transceiver has a first portion in the OMIB and a second portion in one of the dies. The first and the second portions may be coupled via an electrical interconnect less than 2 mm in length. The die includes compute elements around a central region, proximate to the second portion. The OMIB may include an electro-absorption modulator fabricated with germanium, silicon, an alloy of germanium, an alloy of silicon, a III-V material based on indium phosphide (InP), or a III-V material based on gallium arsenide (GaAs). The OMIB may include a temperature compensation for the modulator.

Abstract: A package includes a bridging element (an OMIB), and first and second photonic paths, forming a bidirectional photonic path. The OMIB has first and second interconnect regions to connect with one or more dies. Third and fourth unidirectional photonic paths may couple between the first interconnect region and an optical interface (OI). A photonic transceiver has a first portion in the OMIB and a second portion in one of the dies. The first and the second portions may be coupled via an electrical interconnect less than 2 mm in length. The die includes compute elements around a central region, proximate to the second portion. The OMIB may include an electro-absorption modulator fabricated with germanium, silicon, an alloy of germanium, an alloy of silicon, a III-V material based on indium phosphide (InP), or a III-V material based on gallium arsenide (GaAs). The OMIB may include a temperature compensation for the modulator.

Abstract: Disclosed are coherent photonic circuit architectures that optically implement linear algebraic computations. In neuromorphic applications of such photonic circuit architectures, individual neural network layers can be implemented by coherent optical linear neurons in a crossbar configuration, integrated with electronic circuitry at the interfaces between neural network layers to determine the neuron inputs to one layer based on the neuron outputs of the preceding layer. Wavelength division multiplexing can be used to efficiently implement certain specific network models, optionally in conjunction with electro-optic switches to render a generic hardware configuration programmable.

Abstract: One embodiment is a method that includes generating a request for a data item in a memory, obtaining the data item from the memory with a photonic interface, sending the data item to a fabric using a transmit unit of the photonic interface, and routing the data item through a portion of the fabric coupled to the memory, the portion of the fabric including one or more additional transmit and receive units between the photonic interface and a destination receive unit.

Abstract: A package includes a bridging element (an OMIB), and first and second photonic paths, forming a bidirectional photonic path. The OMIB has first and second interconnect regions to connect with one or more dies. Third and fourth unidirectional photonic paths may couple between the first interconnect region and an optical interface (OI). A photonic transceiver has a first portion in the OMIB and a second portion in one of the dies. The first and the second portions may be coupled via an electrical interconnect less than 2 mm in length. The die includes compute elements around a central region, proximate to the second portion. The OMIB may include an electro-absorption modulator fabricated with germanium, silicon, an alloy of germanium, an alloy of silicon, a III-V material based on indium phosphide (InP), or a III-V material based on gallium arsenide (GaAs). The OMIB may include a temperature compensation for the modulator.

Abstract: The present disclosure relates to thermal control systems, photonic memory fabrics, and electro-absorption modulators (EAMs). For example, the thermal control systems efficiently move data in a memory fabric based on utilizing and controlling thermally controlling optical components. As another example, the EAMs are instances of optical modulators used to efficiently move data within digital circuits while maintaining thermally-stable optical modulation across a wide temperature range.

Abstract: Vector and matrix multiplications can be accomplished in photonic circuitry by coherently combining light that has been optically modulated, in amplitude and/or phase, in accordance with the vector and matrix components. Disclosed are various beneficial photonic circuit layouts characterized by loss- and delay-balanced optical paths. In various embodiments, loss balancing across paths is achieved with suitable optical coupling ratios and balanced numbers of waveguide crossings (using dummy crossings where needed) across the paths. Delays are balanced in some embodiments with geometrically delay-matched optical paths.

Abstract: Vector and matrix multiplications can be accomplished in photonic circuitry by coherently combining light that has been optically modulated, in amplitude and/or phase, in accordance with the vector and matrix components. Disclosed are various beneficial photonic circuit layouts characterized by loss- and delay-balanced optical paths. In various embodiments, loss balancing across paths is achieved with suitable optical coupling ratios and balanced numbers of waveguide crossings (using dummy crossings where needed) across the paths. Delays are balanced in some embodiments with geometrically delay-matched optical paths.

Abstract: Disclosed are coherent photonic circuit architectures that optically implement linear algebraic computations. In neuromorphic applications of such photonic circuit architectures, individual neural network layers can be implemented by coherent optical linear neurons in a crossbar configuration, integrated with electronic circuitry at the interfaces between neural network layers to determine the neuron inputs to one layer based on the neuron outputs of the preceding layer. Wavelength division multiplexing can be used to efficiently implement certain specific network models, optionally in conjunction with electro-optic switches to render a generic hardware configuration programmable.

Abstract: Disclosed are coherent photonic circuit architectures that optically implement linear algebraic computations. In neuromorphic applications of such photonic circuit architectures, individual neural network layers can be implemented by coherent optical linear neurons in a crossbar configuration, integrated with electronic circuitry at the interfaces between neural network layers to determine the neuron inputs to one layer based on the neuron outputs of the preceding layer. Wavelength division multiplexing can be used to efficiently implement certain specific network models, optionally in conjunction with electro-optic switches to render a generic hardware configuration programmable.

Abstract: An embodiment of the present invention sets forth an embedded resistive memory cell that includes a first stack of deposited layers, a second stack of deposited layers, a first electrode disposed under a first portion of the first stack, and a second electrode disposed under a second portion of the first stack and extending from under the second portion of the first stack to under the second stack. The second electrode is disposed proximate to the first electrode within the embedded resistive memory cell. The first stack of deposited layers includes a dielectric layer, a high-k dielectric layer disposed above the dielectric layer, and a metal layer disposed above the high-k dielectric layer. The second stack of deposited layers includes a high-k dielectric layer formed simultaneously with the high-k dielectric layer included in the first stack, and a metal layer disposed above the high-k dielectric layer.

Abstract: A method for analyzing and optimizing fabrication techniques using variations of materials, unit processes, and process sequences is provided. In the method, a subset of a semiconductor manufacturing process sequence and build is analyzed for optimization. During the execution of the subset of the manufacturing process sequence, the materials, unit processes, and process sequence for creating a certain structure is varied. During the combinatorial processing, the materials, unit processes, or process sequence is varied between the discrete regions of a semiconductor substrate, wherein within each of the regions the process yields a substantially uniform or consistent result that is representative of a result of a commercial manufacturing operation. A tool for optimizing a process sequence is also provided.

Abstract: A method for analyzing and optimizing fabrication techniques using variations of materials, unit processes, and process sequences is provided. In the method, a subset of a semiconductor manufacturing process sequence and build is analyzed for optimization. During the execution of the subset of the manufacturing process sequence, the materials, unit processes, and process sequence for creating a certain structure is varied. During the combinatorial processing, the materials, unit processes, or process sequence is varied between the discrete regions of a semiconductor substrate, wherein within each of the regions the process yields a substantially uniform or consistent result that is representative of a result of a commercial manufacturing operation. A tool for optimizing a process sequence is also provided.

Abstract: The present invention provides methods and systems for discretized, combinatorial processing of regions of a substrate such as for the discovery, implementation, optimization, and qualification of new materials, processes, and process sequence integration schemes used in integrated circuit fabrication. A substrate having an array of differentially processed regions thereon is processed by delivering materials to or modifying regions of the substrate.

Abstract: The present invention provides methods and systems for discretized, combinatorial processing of regions of a substrate such as for the discovery, implementation, optimization, and qualification of new materials, processes, and process sequence integration schemes used in integrated circuit fabrication. A substrate having an array of differentially processed regions thereon is processed by delivering materials to or modifying regions of the substrate.

Abstract: The present invention provides methods and systems for discretized, combinatorial processing of regions of a substrate such as for the discovery, implementation, optimization, and qualification of new materials, processes, and process sequence integration schemes used in integrated circuit fabrication. A substrate having an array of differentially processed regions thereon is processed by delivering materials to or modifying regions of the substrate.

Abstract: The present invention provides methods and systems for discretized, combinatorial processing of regions of a substrate such as for the discovery, implementation, optimization, and qualification of new materials, processes, and process sequence integration schemes used in integrated circuit fabrication. A substrate having an array of differentially processed regions thereon is processed by delivering materials to or modifying regions of the substrate.

Abstract: Substrate processing systems and methods are described for processing substrates having two or more regions. The processing includes one or more of molecular self-assembly and combinatorial processing. At least one of materials, processes, processing conditions, material application sequences, and process sequences is different for the processing in at least one region of the substrate relative to at least one other region of the substrate. Processing systems are described that include numerous processing modules. The modules include a site-isolated reactor (SIR) configured for one or more of molecular self-assembly and combinatorial processing of a substrate.