Abstract: In an embodiment, an apparatus includes: a modulator to modulate a first packet according to rate control information; a physical circuit to transmit the modulated first packet according to power control information; and a dynamic adaptation circuit, for the first packet, to provide the rate control information and the power control information of a first modulation and power pair stored in a first energy map.

Abstract: In an embodiment, an apparatus includes: a modulator to modulate a first packet according to rate control information; a physical circuit to transmit the modulated first packet according to power control information; and a dynamic adaptation circuit, for the first packet, to provide the rate control information and the power control information of a first modulation and power pair stored in a first energy map.

Abstract: An apparatus includes a first integrated circuit (IC) that includes a first radio-frequency (RF) circuit to process RF signals, a first antenna port to couple to one or more antennas, and a first switch integrated in the first IC and coupled to the first antenna port. The apparatus further includes a second IC that includes a second RF circuit to process RF signals, a second antenna port to couple to the one or more antennas, and a second switch integrated in the second IC and coupled to the second antenna port.

Abstract: An apparatus includes a first integrated circuit (IC) that includes a first radio-frequency (RF) circuit to process RF signals, a first antenna port to couple to one or more antennas, and a first switch integrated in the first IC and coupled to the first antenna port. The apparatus further includes a second IC that includes a second RF circuit to process RF signals, a second antenna port to couple to the one or more antennas, and a second switch integrated in the second IC and coupled to the second antenna port.

Abstract: An integrated circuit includes a tuner, a digital television (DTV) demodulator, an analog television (ATV) demodulator, and a controller. The tuner includes an input for receiving a radio frequency (RF) signal including at least one of an analog television signal and digital television signal, and including a first output terminal and a second output terminal. The DTV demodulator includes a DTV input coupled to the first output terminal of the tuner and includes a DTV output terminal. The ATV demodulator includes an ATV input coupled to the second output terminal of the tuner and includes an ATV output terminal. The controller is coupled to the tuner, the DTV demodulator, and the ATV demodulator to configure the tuner and at least one of the DTV demodulator and the ATV demodulator for receiving television content in a selected television format.

Abstract: In one embodiment, an interface may include various mechanisms to handle incoming clock and data signals. More specifically, the interface includes a first multiplexer to receive a first data signal via a serial peripheral interface (SPI) bus coupled to a first pin and a second multiplexer to receive a first clock signal via the SPI bus coupled to a second pin of the first IC and a second clock signal via an inter-integrated circuit (I2C) bus coupled to a third pin. In addition, the interface may include a decoder to receive the second clock signal and a second data signal via the I2C bus coupled to a fourth pin.

Abstract: A receiver circuit includes an analog front-end and a digital processing unit. The analog front-end includes an input for receiving a radio frequency (RF) signal, a first control input for receiving a gain adjustment signal, a second control input for receiving a timing signal, and a signal output for providing a digital intermediate frequency (IF) signal. The analog front-end updates gains of a plurality of gain stages according to the gain adjustment signal and in synchronism with the timing signal. The digital processing unit is configured to produce at least one output signal derived from the digital IF signal. The digital processing unit includes a timing recovery circuit configured to generate the timing signal based on the digital IF signal to control timing of the updating gains of each of the plurality of adjustable gain stages.

Abstract: Systems and methods are disclosed for time-domain diversity combining of radio frequency (RF) broadcast signals. Two channelized quadrature (I/Q) signals are generated by different tuner circuitry coupled to two different antennas, are converted to frequency-domain signals, and are used to generate frequency-domain diversity weighting signals. The frequency-domain diversity weighting signals are then converted to time-domain weights and applied to the channelized I/Q signals. The weighted and channelized I/Q signals are then combined in the time-domain to provide a time-domain diversity combined signal. The resulting combined signal can be further processed, as desired, such as by using a demodulator to generate demodulated output signals. Disclosed methods and systems can be applied to a variety of receiver systems configured to receive RF broadcast signals.

Abstract: Systems and methods are disclosed for time-domain diversity combining of radio frequency (RF) broadcast signals. Two channelized quadrature (I/Q) signals are generated by different tuner circuitry coupled to two different antennas, are converted to frequency-domain signals, and are used to generate frequency-domain diversity weighting signals. The frequency-domain diversity weighting signals are then converted to time-domain weights and applied to the channelized I/Q signals. The weighted and channelized I/Q signals are then combined in the time-domain to provide a time-domain diversity combined signal. The resulting combined signal can be further processed, as desired, such as by using a demodulator to generate demodulated output signals. Disclosed methods and systems can be applied to a variety of receiver systems configured to receive RF broadcast signals.

Abstract: In one embodiment, an interface may include various mechanisms to handle incoming clock and data signals. More specifically, the interface includes a first multiplexer to receive a first data signal via a serial peripheral interface (SPI) bus coupled to a first pin and a second multiplexer to receive a first clock signal via the SPI bus coupled to a second pin of the first IC and a second clock signal via an inter-integrated circuit (I2C) bus coupled to a third pin. In addition, the interface may include a decoder to receive the second clock signal and a second data signal via the I2C bus coupled to a fourth pin.

Abstract: An integrated circuit includes a tuner, a digital television (DTV) demodulator, an analog television (ATV) demodulator, and a controller. The tuner includes an input for receiving a radio frequency (RF) signal including at least one of an analog television signal and digital television signal, and including a first output terminal and a second output terminal. The DTV demodulator includes a DTV input coupled to the first output terminal of the tuner and includes a DTV output terminal. The ATV demodulator includes an ATV input coupled to the second output terminal of the tuner and includes an ATV output terminal. The controller is coupled to the tuner, the DTV demodulator, and the ATV demodulator to configure the tuner and at least one of the DTV demodulator and the ATV demodulator for receiving television content in a selected television format.

Abstract: A receiver circuit includes an analog front-end and a digital processing unit. The analog front-end includes an input for receiving a radio frequency (RF) signal, a first control input for receiving a gain adjustment signal, a second control input for receiving a timing signal, and a signal output for providing a digital intermediate frequency (IF) signal. The analog front-end updates gains of a plurality of gain stages according to the gain adjustment signal and in synchronism with the timing signal. The digital processing unit is configured to produce at least one output signal derived from the digital IF signal. The digital processing unit includes a timing recovery circuit configured to generate the timing signal based on the digital IF signal to control timing of the updating gains of each of the plurality of adjustable gain stages.

Abstract: The transmission system is backward compatible with a former transmission system (DVB-T), enabling a receiver of the former system to receive signals transmitted by a transmitter of the new transmission system. A new modulation is used to transmit additional information bits corresponding to a new service. The new modulation is specified by a combination of the former modulation with a new-built over modulation.

Abstract: The invention relates to a testing apparatus (21) comprising means for receiving signals in a frequency range comprising a plurality of channels. The testing apparatus further comprises means for scanning said frequency range (210, 213), means for detecting at least one channel comprising a digital signal (211), means for measuring a bit error rate of said digital signal (212), means for performing at least one comparison between said bit error rate and at least one threshold (213), and means for determining a quality of said channel on the basis of said comparison.

Abstract: The transmission system is backward compatible with a former transmission system (DVB-T), enabling a receiver of the former system to receive signals transmitted by a transmitter of the new transmission system. A new modulation is used to transmit additional information bits corresponding to a new service. The new modulation is specified by a combination of the former modulation with a new-built over modulation.