Abstract: A method and apparatus for establishing multiple network sessions over an arbitrary network topology comprises receiving network configuration information describing an initiator system and a target controller. The initiator system contains one or more initiator ports. The target controller contains one or more target ports. Each target port is associated with one or more target nodes. A set of pre-defined rules is identified. The set of pre-defined rules governs the establishment of network sessions between the initiator ports and the target nodes through the target ports. One or more network sessions are established based on the set of pre-defined rules and the network configuration information.

Abstract: A method and apparatus for establishing multiple network sessions over an arbitrary network topology comprises receiving network configuration information describing an initiator system and a target controller. The initiator system contains one or more initiator ports. The target controller contains one or more target ports. Each target port is associated with one or more target nodes. A set of pre-defined rules is identified. The set of pre-defined rules governs the establishment of network sessions between the initiator ports and the target nodes through the target ports. One or more network sessions are established based on the set of pre-defined rules and the network configuration information.

Abstract: A method and apparatus are provided for mapping multiple address spaces into a single bus, such as a single peripheral component interconnect (PCI) bus. The single bus is coupled to a first processor complex and a second processor complex. An original address of a memory access is shifted to a unique address space for each originator/target of an operation. The shifted address is used on the single bus. Then the shifted address is shifted back to the original address for completing the operation on a destination bus. The original address of a memory access is shifted to a unique address space for each originator/target of an operation using a respective predefined value (+X1, +X2, or +X3) for shifting the original address above a predefined boundary for each originator/target of the operation.

Abstract: A method and apparatus are provided for interrupt routing of peripheral component interconnect (PCI) adapters via device address mapping. A first processor complex includes a multifunction PCI to PCI bridge interface chip. A local PCI bus is coupled between a second processor complex and the multifunction PCI to PCI bridge interface chip. A host PCI bus is coupled between the multifunction PCI to PCI bridge interface chip and a second multifunction PCI to PCI bridge chip. A plurality of local area network (LAN) adapters are coupled to the second multifunction PCI to PCI bridge chip. The multifunction PCI to PCI bridge interface chip of the first processor complex includes interrupt mapping logic for mapping interrupts from the LAN adapters to PCI interrupts on the local PCI bus to the second processor complex.

Abstract: In an electrical system having a connector board with at least one electrical connector thereon for receiving an electrical device therein, volumetric vital product parametric data is stored in memory associated with the connector board. The stored volumetric vital product parametric data can be accessed with the electrical system to check for available space for a proposed electrical device, for example. The stored data may include information about dimensional characteristics of the connector board and the at least one electrical connector. This data can be compared with corresponding data for the electrical device to determine compatibility, for example.

Abstract: A method and apparatus are provided for interrupt routing of peripheral component interconnect (PCI) adapters via device address mapping. A first processor complex includes a multifunction PCI to PCI bridge interface chip. A first local PCI bus is coupled between a second processor complex and the multifunction PCI to PCI bridge interface chip. A second host PCI bus is coupled between the multifunction PCI to PCI bridge interface chip and a second multifunction PCI to PCI bridge chip. A plurality of local area network (LAN) adapters are coupled to the second multifunction PCI to PCI bridge chip. The multifunction PCI to PCI bridge interface chip of the first processor complex includes interrupt mapping logic for mapping interrupts from the LAN adapters to PCI interrupts on the local PCI bus to the second processor complex.

Abstract: An adapter node is provided for use in adapting internal system enclosure services to a system power control network to thereby provide remote power control, diagnostics, and logical-to-physical correlation information, through the system power control network. The adapter node is for use in one computer of a plurality of different types of computers, having a respective internal system enclosure services low-level communication path. The power control network has a plurality of nodes, one of the nodes being a control node. The adapter node includes a substrate having electrical contacts adapted to plug to a system bus in the one computer. The substrate further has at least one system enclosure services interface connection to connect to the internal system enclosure services low-level communication path in the one computer. The adapter node further has a system power control network interface connection for connecting to the system power control network.