Abstract: Techniques and devices for level-shifting a signal are described. A level-shifting circuit may include an input terminal and components. The input terminal may be configured to receive a logical signal compatible with a first power domain. The components may be configured to convert the logical signal to a second power domain and to provide the converted logical signal at an output terminal. The components may include a resistive device coupled between the output terminal and the input terminal, and/or a capacitive device coupled between the resistive device and the input terminal.

Abstract: Disclosed are devices, apparatus, circuitry, components, mechanisms, modules, units, systems, and processes for controlling a power switch of a voltage regulator. A capacitor is coupled to an output of the power switch. Charge delivery circuitry is coupled to the capacitor and configured to provide a charging current to the capacitor. Charge control circuitry can be coupled to the charge delivery circuitry and configured to selectively allow the providing of the charging current to the capacitor.

Abstract: A switched-mode power regulator circuit has four solid-state switches connected in series and a capacitor and an inductor that regulate power delivered to a load. The solid-state switches are operated such that a voltage at the load is regulated by repetitively (1) charging the capacitor causing a current to flow in the inductor and (2) discharging the capacitor causing current to flow in the inductor. The power regulator circuit may be configured to operate with zero current switching at frequencies in the range of 100 MHz, enabling it to be fabricated on a unitary silicon die along with the load that it powers.

Abstract: Disclosed are devices, apparatus, circuitry, components, mechanisms, modules, units, systems, and processes for controlling the switching frequency of a voltage regulator. Frequency monitoring and adjustment circuitry is coupled to sense a switching frequency of a power switch coupled to an output filter of the voltage regulator. The frequency monitoring and adjustment circuitry is configured to provide a frequency adjustment signal based on the sensed switching frequency. Power switch control circuitry is coupled to receive the frequency adjustment signal and is configured to control switching of the power switch based on the frequency adjustment signal.

Abstract: Disclosed are systems, devices, circuits, components, mechanisms, and processes in which a switching mechanism can be coupled between components. The switching mechanism is configured to have an on state or an off state, where the on state allows current to pass along a current path. A monitoring mechanism has one or more sensing inputs coupled to sense an electrical characteristic at the current path. The electrical characteristic can be a current, voltage, and/or power by way of example. The monitoring mechanism is configured to output a reporting signal indicating the sensed electrical characteristic. The monitoring mechanism can be integrated with the switching mechanism on a chip.

Abstract: A detection circuit and one or more wires or circuit traces are included in a die. The combination is used to detect mechanical failure of the substrate, e.g. silicon after singulation of the dice from the wafer. Failures may be detected at different regions or planes within the die, and the tests may be performed during operation of the packaged die and integrated circuit, even after installation and during operation of a larger electronic device in which it is incorporated. This is especially useful for chip scale packages, but may be utilized in any type of IC package.

Abstract: Disclosed are devices, apparatus, circuitry, components, mechanisms, modules, units, systems, and processes for controlling a power switch of a voltage regulator. A capacitor is coupled to an output of the power switch. Charge delivery circuitry is coupled to the capacitor and configured to provide a charging current to the capacitor. Charge control circuitry can be coupled to the charge delivery circuitry and configured to selectively allow the providing of the charging current to the capacitor.

Abstract: Disclosed are devices, apparatus, circuitry, components, mechanisms, modules, units, systems, and processes for controlling the switching frequency of a voltage regulator. Frequency monitoring and adjustment circuitry is coupled to sense a switching frequency of a power switch coupled to an output filter of the voltage regulator. The frequency monitoring and adjustment circuitry is configured to provide a frequency adjustment signal based on the sensed switching frequency. Power switch control circuitry is coupled to receive the frequency adjustment signal and is configured to control switching of the power switch based on the frequency adjustment signal.

Abstract: Methods and apparatus for measuring an optical azimuth angle ?O of a substrate relative to a plane of detection in scatterometry tools are disclosed. A grating target on a stage of a scatterometry tool may be illuminated and positions of the resulting diffraction orders may be observed. The optical azimuth angle may be determined from the positions of the diffraction orders. Alternatively, polarization-dependent signals of radiation scattered from a line grating may be measured for equal and opposite polarization angles +A and ?A. A combination signal may be computed from the polarization-dependent signals obtained at +A and ?A and a property of the combination signal may be calculated for several mechanical Azimuth angles ?M. A relationship between the optical azimuth angle ?O and the mechanical azimuth angle ?M may be determined from a behavior of the property as a function of mechanical azimuth angle ?M.

Abstract: A detection circuit and one or more wires or circuit traces are included in a die. The combination is used to detect mechanical failure of the substrate, e.g. silicon after singulation of the dice from the wafer. Failures may be detected at different regions or planes within the die, and the tests may be performed during operation of the packaged die and integrated circuit, even after installation and during operation of a larger electronic device in which it is incorporated. This is especially useful for chip scale packages, but may be utilized in any type of IC package.

Abstract: A multi-phase, coupled-inductor, DC-DC voltage converter operates in discontinuous conduction mode (DCM) when the system is operated at low output power demand. An embodiment of the converter switches to operating in continuous conduction mode (CCM) when the system is operated at high output power demand. Operation in single-drive and rotating phase DCM operation at low power are described. An alternative embodiment operates in a multiple-drive, rotating-phase, discontinuous conduction mode during at least one condition of output power demand.

Abstract: A multi-phase, coupled-inductor, DC-DC voltage converter operates in discontinuous conduction mode (DCM) when the system is operated at low output power demand. An embodiment of the converter switches to operating in continuous conduction mode (CCM) when the system is operated at high output power demand. Operation in single-drive and rotating phase DCM operation at low power are described. An alternative embodiment operates in a multiple-drive, rotating-phase, discontinuous conduction mode during at least one condition of output power demand.

Abstract: A multi-phase, coupled-inductor, DC-DC voltage converter operates in discontinuous conduction mode (DCM) when the system is operated at low output power demand. An embodiment of the converter switches to operating in continuous conduction mode (CCM) when the system is operated at high output power demand. Operation in single-drive and rotating phase DCM operation at low power are described. An alternative embodiment operates in a multiple-drive, rotating-phase, discontinuous conduction mode during at least one condition of output power demand.

Abstract: A system, method and device for AO2R is presented. The AO2R system presented is redundant, containing multiple pathways for the input and output signals to travel. The system carries out both the regeneration and reshaping functions in the optical domain, and returns a clean output signal at the same bit rate and in the same format as the input signal, on a wavelength of choice. As an all optical device, the apparatus is bit rate and format transparent, and requires no optical-electrical-optical conversion. The system's built in redundancy and symmetry allows less than perfect yields on components to be tolerated, thus increasing the utility of devices manufactured with less than perfect yields. In alternative embodiments the redundancy aspect of the invention can be extended to any optical signal processing device, thus facilitating high availability optical signal processing.

Abstract: A method and apparatus for a tunable optical spectrum analyzer that can measure the optical spectrum of a demultiplexed DWDM signal are presented. The signal level and Optical Signal to Noise Ratio (OSNR) of an individual channel of the DWDM signal can be obtained from the measured optical spectrum. The device employs a rapid tuning and detection technique to obtain the optical spectrum of the incoming signal. In a preferred embodiment the apparatus is fabricated on a single chip resulting in a compact measurement device. Using the device of the preferred embodiment, single channel OSNR can be determined in as small a time interval as approximately 225 microseconds. Using an array of these devices an entire DWDM mixed signal can be monitored as to OP and OSNR in the same time interval.

Abstract: A method and apparatus for determining a setting specified from a plurality of the settings for a function provided in an integrated circuit, wherein the setting is specified by connecting an external measurement resistor to a measurement terminal of the integrated circuit, comprises applying a direct current to the measurement terminal of the integrated circuit, thereby producing a measurement voltage at the measurement terminal; applying the direct current to a reference terminal of the integrated circuit, wherein the reference terminal has an external reference resistor connected thereto, thereby producing a reference voltage at the reference terminal; quantizing a voltage level of a difference voltage representing a voltage difference between the reference voltage and the measurement voltage, thereby producing a quantized voltage; and providing control signals to a functional module within the integrated circuit, the control signals representing the one of the settings corresponding to the quantized volta

Abstract: A single device for amplifying and multiplying an optical signal is presented. The device is an InP-semiconductor-based amplified multimode interferometer. The three main sections of the device are an input port, an interference and amplification region and N output ports. The input port is a single channel waveguide. The interference and amplification section supports a large number of modes which interfere with one another. By carefully choosing the length of the interference/amplification region to correspond to the constructive interference condition for N equally spaced channel modes, we can reproduce N amplified signals. In an alternate embodiment, by shaping the gain region into a cross pattern, corner reflections and consequent side channel signal distortion in the output can be minimized.

Abstract: A method and circuit are presented for an all-optical format independent preprocessor that processes an arbitrary optical input signal by converting a NRZ signal to a PRZ signal, or if the input optical signal is RZ, by merely amplifying it. The method involves subtracting a delayed copy of the signal from the original, thereby effectively doubling its frequency, and inserting a pulse at each transition of the original signal, whether rising or falling. In a preferred embodiment this stage is implemented via an integrated SOA in each arm of an asymmetric interferometric device. The asymmetry consists of a delay element in one arm. In a preferred embodiment the entire device is fabricated on a semiconductor substrate, allowing for compactness as well as minimization of interconnectivity losses and overall power consumption. The output of the preprocessor, having a significant frequency component at its original clock rate, can then be fed to a clock recovery stage for all-optical clock recovery.

Abstract: A method and circuit are presented for an all-optical format independent preprocessor that processes an arbitrary optical input signal by converting a NRZ signal to a PRZ signal, or if the input optical signal is RZ, by merely amplifying it. The method involves subtracting a delayed copy of the signal from the original, thereby effectively doubling its frequency, and inserting a pulse at each transition of the original signal, whether rising or falling. In a preferred embodiment this stage is implemented via an integrated SOA in each arm of an asymmetric interferometric device. The asymmetry consists of a delay element in one arm. In a preferred embodiment the entire device is fabricated on a semiconductor substrate, allowing for compactness as well as minimization of interconnectivity losses and overall power consumption. The output of the preprocessor, having a significant frequency component at its original clock rate, can then be fed to a clock recovery stage for all-optical clock recovery.

Abstract: A method and circuit are presented for an all-optical format independent preprocessor that processes an arbitrary optical input signal by converting a NRZ signal to a PRZ signal, or if the input optical signal is RZ, by merely amplifying it. The method involves subtracting a delayed copy of the signal from the original, thereby effectively doubling its frequency, and inserting a pulse at each transition of the original signal, whether rising or falling. In a preferred embodiment this stage is implemented via an integrated SOA in each arm of an asymmetric interferometric device. The asymmetry consists of a delay element in one arm. In a preferred embodiment the entire device is fabricated on a semiconductor substrate, allowing for compactness as well as minimization of interconnectivity losses and overall power consumption. The output of the preprocessor, having a significant frequency component at its original clock rate, can then be fed to a clock recovery stage for all-optical clock recovery.