Abstract: Digital remodulation systems typically include digital to analog converters which have an inherent undesirable sin(x)/x frequency response. Digital remodulated signals are typically high frequency and thus not conducive to sin(x)/x pre-correction prior to digital to analog conversion. Described herein is apparatus and a method for pre-correcting the sin(x)/x roll off of the digital to analog converter in the digital signal path prior to the digital modulator which precedes the digital to analog converter. This apparatus corresponds to a cascading of spectrally symmetric and anti-symmetric transversal filters designed to compensate a relatively small portion of the frequency response of the resulting analog signal.

Abstract: A method for generating digital carrier signals for application as the carrier to a digital modulator includes providing a first repeating sequence of complex values occurring at a given sample rate and upsampling these values to a higher sample rate. A second repeating sequence of complex values is provided, wherein respective complex values in the second repeating sequence occur at the higher sample rate. The second sequence of complex values is employed to modulate the upsampled first sequence of complex values and thereby provide the complex carrier signal.

Abstract: A sample rate conversion system converts data of a first sample rate to data of a different second sample rate. The system involves an interpolator, operating at the first sample rate and includes a first interpolation network and a delay network. The first interpolation network interpolates the first sample rate data to provide upsampled interpolated data samples according to a first sample spacing. The delay network interpolates the upsampled interpolated data to provide delayed upsampled interpolated data samples, according to a second sample spacing of higher resolution than the first sample spacing, and preceding and succeeding an original sample position. The system also includes a digital filter operating at the second sample rate for filtering the higher resolution data samples to provide the second sample rate data.

Abstract: A digital VSB modulator includes a modulator to which an ongoing sampled data stream of 1-sample-per-symbol successive PCM symbol signal samples are applied as a modulating signal. A sampled carrier stream, occurring at the rate of the signal samples, is applied as a carrier input to the modulator. The carrier stream is composed of, for example, a repeated 4-sample-sequence of 1, −1, −1, 1 sample values. The output of the modulator is applied to a bifurcated multiplexed N-tap root Nyquist FIR filter, which produces a VSB bifurcated complex output signal having a DC-centered real (±R) sampled data output stream of 1-sample-per-symbol sample values and a DC-centered imaginary (±I) sampled data output stream of 1-sample-per-symbol sample values.

Abstract: A timing recovery system for a digital signal receiver receives a signal, representing successive symbols, from a transmitter. The symbols are subject to exhibiting multiple symbol rates. The system derives a sample enable signal from the received input signal and employs a single, fixed frequency oscillator. A source of samples representing the received signal are sampled at a fixed frequency. An interpolator is coupled to the sample source and is responsive to a control signal. The interpolator produces samples taken at times synchronized to the successive symbols from the transmitter. A phase error detector is coupled to the interpolator, detects a phase error between the sample times of the transmitter synchronized samples produced by the interpolator and times of the successive transmitter symbols, and supplies a phase error signal. The phase error signal is coupled to one input terminal of a summer and a source of a nominal delay signal is coupled to the other.

Abstract: A receiver is arranged for receiving a transmitted quadrature amplitude modulated (QAM) signal representing successive symbols, and including an in-phase (I) component and a quadrature (Q) component. In such a receiver, a timing recovery system includes a source of samples representing the QAM signal produced at a fixed frequency. A first chain of processing circuitry for the I component includes a first demodulator, coupled to the sample source, for demodulating the I component of the QAM signal to baseband; and a first interpolator, coupled to the first demodulator and responsive to a control signal, for producing I component samples taken at times synchronized to the transmitted symbols.

Abstract: A filtering circuit suitable for use in a video sample rate converter provides a constant direct current (DC) gain irrespective of realization errors, and reduces hardware requirements. The circuit includes an input terminal for receiving an input signal. A first delay unit delays the input signal to generate a first delayed signal. A subtracting unit subtracts the input signal from the first delayed signal to generate a difference signal. A second delay unit delays the difference signal to generate a second delayed signal. A reference delay unit delays the first delayed signal by a predetermined reference time period to generate a reference signal. A filtering unit filters the second delayed signal to generate a filtered signal. An adding unit adds the reference signal to the filtered signal to generate an output signal.