Patents by Inventor DAVID LYLE KIRK

DAVID LYLE KIRK has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Bus bridge for translating requests between a module bus and an axi bus
    Patent number: 10216669
    Abstract: A method for bus bridging includes providing a bus interface device that is coupled between at least one module bus and at least one advanced extensible interface (AXI) bus for translating bus requests between the module bus and the AXI bus. The bus interface device includes logic. The logic is configured to receive a read/write (R/W) request that is one of a module bus protocol R/W request and an AXI bus protocol R/W request and to buffer the R/W request to provide a buffered R/W request. The logic translates the buffered R/W request to a first AXI protocol conforming request if the buffered R/W request is the module bus protocol R/W request and translates the buffered R/W request to a first module bus protocol conforming request if the buffered R/W request is the AXI bus protocol R/W request. The translated requests are transmitted to their respective bus.
    Type: Grant
    Filed: February 23, 2016
    Date of Patent: February 26, 2019
    Assignee: Honeywell International Inc.
    Inventors: Sameer D. Manikfan, David Lyle Kirk, Jay W. Gustin
  • BUS BRIDGE FOR TRANSLATING REQUESTS BETWEEN A MODULE BUS AND AN AXI BUS
    Publication number: 20170242813
    Abstract: A method for bus bridging includes providing a bus interface device that is coupled between at least one module bus and at least one advanced extensible interface (AXI) bus for translating bus requests between the module bus and the AXI bus. The bus interface device includes logic. The logic is configured to receive a read/write (R/W) request that is one of a module bus protocol R/W request and an AXI bus protocol R/W request and to buffer the R/W request to provide a buffered R/W request. The logic translates the buffered R/W request to a first AXI protocol conforming request if the buffered R/W request is the module bus protocol R/W request and translates the buffered R/W request to a first module bus protocol conforming request if the buffered R/W request is the AXI bus protocol R/W request. The translated requests are transmitted to their respective bus.
    Type: Application
    Filed: February 23, 2016
    Publication date: August 24, 2017
    Inventors: SAMEER D. MANIKFAN, DAVID LYLE KIRK, JAY W. GUSTIN