Abstract: A computer-implemented method for designing an integrated circuit includes determining a timing slack associated with a first cell of the integrated circuit that is physically adjacent to a second cell of the integrated circuit, the second cell including an implant region that is in violation of an implant width design rule associated with the integrated circuit, determining that the timing slack is greater than a change in timing slack associated with expanding the implant region into the first cell, and, in response, expanding the implant region from first cell into the second cell to form a larger implant region.

Abstract: One embodiment of the present invention includes a method for updating timing parameters after a circuit design change. The method includes, prior to the circuit design change, deriving a value for a first timing parameter based on a signoff timing analysis of a timing arc, and a value for a second timing parameter based on a quick timing analysis of the timing arc; and obtaining a first transition time based on the quick timing analysis. The method further includes, after the circuit design change, deriving a value for a third timing parameter based on the quick timing analysis, obtaining a second transition time based on the quick timing analysis, and deriving a fourth value for a fourth parameter based on the quick timing analysis, wherein the fourth parameter is based on the first, second, and third parameters and on the first and second transition times.

Abstract: One embodiment of the present invention includes a method for updating timing parameters after a circuit design change. The method includes, prior to the circuit design change, deriving a value for a first timing parameter based on a signoff timing analysis of a timing arc, and a value for a second timing parameter based on a quick timing analysis of the timing arc; and obtaining a first transition time based on the quick timing analysis. The method further includes, after the circuit design change, deriving a value for a third timing parameter based on the quick timing analysis, obtaining a second transition time based on the quick timing analysis, and deriving a fourth value for a fourth parameter based on the quick timing analysis, wherein the fourth parameter is based on the first, second, and third parameters and on the first and second transition times.

Abstract: A computer-implemented method for designing an integrated circuit includes determining a timing slack associated with a first cell of the integrated circuit that is physically adjacent to a second cell of the integrated circuit, the second cell including an implant region that is in violation of an implant width design rule associated with the integrated circuit, determining that the timing slack is greater than a change in timing slack associated with expanding the implant region into the first cell, and, in response, expanding the implant region from first cell into the second cell to form a larger implant region.

Abstract: A method for performing an interface analysis. The method includes identifying a first module included in a representation of a digital circuit. The method also includes identifying a first output port associated with the first module. The method further includes identifying a first logic path that extends from the first output port. The method also includes determining that the first logic path extends to a first storage element included in the first module. The method further includes including the first module, the first output port, the first logic path, and the first storage element in interface logic output data.

Abstract: Techniques are described for semiconductor chips with reduced capacitive power dissipation as a result of improved conductor line spacing. The approaches are particularly applicable to 0.25 micron chip design processes and below. According to one aspect, where there are n available metallization layers available to the designer, a smaller number of layers, such as n−1, are utilized initially in developing a routing design. Then, at least one further metallization layer is used to systematically route conductors, such as bus conductors, to increase the number of metal pitches between conductors, by promoting conductors from one layer to another.

Abstract: Techniques are described for semiconductor chips with reduced capacitive power dissipation as a result of improved conductor line spacing. The approaches are particularly applicable to 0.25 micron chip design processes and below. According to one aspect, where there are n available metallization layers available to the designer, a smaller number of layers, such as n-1, are utilized initially in developing a routing design. Then, at least one further metallization layer is used to systematically route conductors, such as bus conductors, to increase the number of metal pitches between conductors, by promoting conductors from one layer to another.