Abstract: In an example, a method of manufacturing a semiconductor device includes providing a semiconductor substrate comprising an unpolished CZ silicon substrate, a substrate upper side, and a substrate lower side opposite to the substrate upper side. The method includes first annealing the semiconductor substrate at a first temperature in an inert environment for a first time. The method includes second annealing the semiconductor substrate at a second temperature in a wet oxidation environment for a second time. The first annealing dissolves inner wall oxide in bulk region voids and the second annealing fills the voids with semiconductor interstitials. In some examples, the CZ silicon substrate is provided from a CZ ingot grown in the presence of a magnetic field and using continuous counter-doping. The method provides, among other things, a CZ silicon substrate with reduced crystal originated particle (COP) defects, reduced oxygen concentration, and reduced radial resistivity variation.

Abstract: A method of forming a semiconductor device includes providing a semiconductor substrate and forming amorphous semiconductor layers adjacent a major surface of the substrate. The method includes interposing dielectric layers between the amorphous semiconductor layers. The method includes forming polycrystalline semiconductor layers adjacent the amorphous semiconductor layers. The method includes interposing dielectric layers between the polycrystalline semiconductor layers and between the last amorphous semiconductor layer and the first polycrystalline semiconductor layer. The method includes forming a fine-grain polycrystalline semiconductor layer adjacent the polycrystalline semiconductor layers but is separated from the last polycrystalline semiconductor layer by an additional dielectric layer. The fine-grain polycrystalline semiconductor layer is formed at a higher temperature than the polycrystalline semiconductor layers and the amorphous semiconductor layers.

Abstract: In one embodiment, methods for making semiconductor devices are disclosed.

Abstract: At least one exemplary embodiment is directed to a method of forming a multilayered gettering structure that can be used to control wafer warpage.

Abstract: In one embodiment, methods for making semiconductor devices are disclosed.

Abstract: At least one exemplary embodiment is directed to a method of forming a multilayered Bettering structure that can be used to control wafer warpage.

Abstract: In one embodiment, a multi-layer extrinsic gettering structure includes plurality of polycrystalline semiconductor layers each separated by a dielectric layer.

Abstract: In one embodiment, a multi-layer extrinsic gettering structure includes plurality of polycrystalline semiconductor layers each separated by a dielectric layer.