Abstract: Packets are processed while maintaining a sequence of the packets. Packets are received and a sequence identifier assigned to the packets. The sequence identifier specifies a serial order associated with the packet. The packets are provided to a plurality of parallel packet transform processors and the packets are processed utilizing the packet transform processors. The processed packets are ordered based on the sequence identifier of the packets. The packets may be evaluated to classify the packets so as to identify related packets. A sequence identifier is assigned to the packets such that the sequence identifier identifies an ordering of the related packets. The processed packets are ordered based on the classification of the packets and the sequence identifier of the packets. Parallel packet transform processing may be particularly well suite to parallel cryptographic processing.

Abstract: A digital pulsed phase locked loop (DPPLL) provides exact measurements of echo phase, time, and/or position delay as well as echo amplitude. These exact measurements provide better and more reliable results that directly benefit the many real world applications for the DPPLL. The DPPLL permits simultaneous tracking of multiple echo pulses and considerably improved echo selection and sampling.

Abstract: Montgomery exponentiators and methods modulo exponentiate a generator (g) to a power of an exponent (e). The Montgomery exponentiators and methods include a first multiplier that is configured to repeatedly square a residue of the generator, to produce a series of first multiplier output values at a first multiplier output. A second multiplier is configured to multiply selected ones of the series of first multiplier output values that correspond to a bit of the exponent that is binary one, by a partial result, to produce a series of second multiplier output values at a second multiplier output. By providing two multipliers that are serially coupled as described above, Montgomery exponentiation can be accelerated.

Abstract: Montgomery multipliers and methods modular multiply a residue multiplicand by a residue multiplier to obtain a residue product, using a scalar multiplier, a first vector multiplier and a second vector multiplier. A controller is configured to control the scalar multiplier, the first vector multiplier and the second vector multiplier, to overlap scalar multiplies using a selected digit of the multiplier and vector multiplies using a modulus and the multiplicand. The scalar multiplier is configured to multiply a least significant digit of the multiplicand by a first selected digit of the multiplier, to produce a scalar multiplier output. The first vector multiplier is configured to multiply the scalar multiplier output by a modulus, to produce a first vector multiplier output. The second vector multiplier is configured to multiply a second selected digit of the multiplier by the multiplicand, to produce a second vector multiplier output.

Abstract: A packet is processed by encapsulating the packet with a packet-object header if the packet does not have a packet-object header. The encapsulated packet is processed based on information contained in the packet-object header using a plurality of transform modules that are coupled to each other in a series or pipeline configuration. The plurality of transform modules process the encapsulated packet independent of each other.

Abstract: Packets are processed while maintaining a sequence of the packets. Packets are received and a sequence identifier assigned to the packets. The sequence identifier specifies a serial order associated with the packet. The packets are provided to a plurality of parallel packet transform processors and the packets are processed utilizing the packet transform processors. The processed packets are ordered based on the sequence identifier of the packets. The packets may be evaluated to classify the packets so as to identify related packets. A sequence identifier is assigned to the packets such that the sequence identifier identifies an ordering of the related packets. The processed packets are ordered based on the classification of the packets and the sequence identifier of the packets. Parallel packet transform processing may be particularly well suite to parallel cryptographic processing.

Abstract: Parallel generation of random values of a stream cipher utilizing a common S-box is provided. The generation of the values includes determining if a collision exists between accesses of the common S-box. The determination of the two sequential random values is then modified based on whether a collision exists between accesses of the common S-box. The stream cipher may be the ARC-4 cipher.

Abstract: Montgomery multipliers and methods modular multiply a residue multiplicand by a residue multiplier to obtain a residue product, using a scalar multiplier, a first vector multiplier and a second vector multiplier. A controller is configured to control the scalar multiplier, the first vector multiplier and the second vector multiplier, to overlap scalar multiplies using a selected digit of the multiplier and vector multiplies using a modulus and the multiplicand. The scalar multiplier is configured to multiply a least significant digit of the multiplicand by a first selected digit of the multiplier, to produce a scalar multiplier output. The first vector multiplier is configured to multiply the scalar multiplier output by a modulus, to produce a first vector multiplier output. The second vector multiplier is configured to multiply a second selected digit of the multiplier by the multiplicand, to produce a second vector multiplier output.

Abstract: Montgomery exponentiators and methods modulo exponentiate a generator (g) to a power of an exponent (e). The Montgomery exponentiators and methods include a first multiplier that is configured to repeatedly square a residue of the generator, to produce a series of first multiplier output values at a first multiplier output. A second multiplier is configured to multiply selected ones of the series of first multiplier output values that correspond to a bit of the exponent that is binary one, by a partial result, to produce a series of second multiplier output values at a second multiplier output. By providing two multipliers that are serially coupled as described above, Montgomery exponentiation can be accelerated.

Abstract: Embodiments of cryptographic data processing systems, computer program products, and methods of operating same are provided. For example, cryptographic data processing systems include a host processor, a system memory coupled to the host processor, and a cryptographic processor integrated circuit that comprises a local memory. One or more operands are downloaded into the local memory from the system memory and the cryptographic processor executes an instruction that references one of the downloaded operands using a first relative position in the local memory. Operands and results may be packed together in the local memory, which may conserve storage space. In other embodiments, separate command interfaces are provided that are respectively associated with execution units in the cryptographic processor. Commands blocks are respectively provided to the execution units and these command blocks are executed simultaneously by the plurality of execution units.

Abstract: Embodiments of cryptographic data processing systems, computer program products, and methods of operating same are provided in which system memory is used to transfer information between a host processor and an adjunct processor.

Abstract: A real time three dimensional ultrasound imaging probe apparatus is configured to be placed inside a body. The apparatus comprises an elongated body having proximal and distal ends with an ultrasonic transducer phased array connected to and positioned on the distal end of the elongated body. The ultrasonic transducer phased array is positioned to emit and receive ultrasonic energy for volumetric forward scanning from the distal end of the elongated body. The ultrasonic transducer phased array includes a plurality of sites occupied by ultrasonic transducer elements. At least one ultrasonic transducer element is absent from at least one of the sites, thereby defining an interstitial site. A tool is positioned at the interstitial site. In particular, the tool can be a fiber optic lead, a suction tool, a guide wire, an electrophysiological electrode, or an ablation electrode. Related systems are also discussed.

Abstract: In accordance with the present invention, a technique for efficiently utilizing memory in determining which next state accumulated cost to retain, such as in a communication system or a Viterbi decoder. The system includes a memory having a portion of registers allocated to a first array and a portion of registers allocated to a second array. The technique includes retrieving a present state accumulated cost from a storage register of the first array and calculating a next state accumulated cost based on the present state accumulated cost. The next state accumulated cost is stored in a storage register of the second array. The second array is designated as containing present state accumulated costs. A present state accumulated cost is retrieved from a storage register of the second array and used in calculating a subsequent next state accumulated cost. The subsequent next state accumulated cost is stored in a storage register of the first array.

Abstract: A digital signal processor with an embedded error correcting coprocessor (ECCP) is disclosed. The ECCP provides soft symbol Viterbi decoded outputs which have the absolute value of the accumulated cost difference of competing states concatenated with the traceback bit or most significant bit of the next state.

Abstract: A high speed method for presenting display of images obtained from a volumetric scanner in which multiple slices of object space are displayed simultaneously in real time thereby enabling a viewer to study relationships between various parts of the object. The slices are selectable by the viewer manipulating an icon on the display screen. Accordingly C-scans or B scans may be selected as well as I scans in which the scan plane has a selected orientation. Multiple I scans may be selected and viewed in perspective so that the viewer has an impression of a three dimensional display. Color and spectral doppler is incorporated with the scans to provide additional information of dynamic properties.

Abstract: A digital communication system including Viterbi decoder for tracing a path through a trellis of individual state information and method of operation are disclosed. The traceback determines a decoded symbol. The trellis of surviving branch data is stored in an array of registers. Operating the system includes initiating a first traceback from a storage register at a first symbol instant. The traceback traces a path back through the trellis a first predetermined number of symbol instants to determine a first decoded symbol. A second traceback is also initiated at the first symbol instant and traces a path back through the trellis a second predetermined number symbol instants to determine a second decoded symbol. The first traceback length may be greater than or less than the second traceback length. In another embodiment of the invention several tracebacks can be executed having a fixed traceback length, followed by other tracebacks having incrementally different traceback lengths.

Abstract: A communication system including a Viterbi decoder for tracing a path through a trellis of individual state information and method of operation are disclosed. The traceback determines a decoded symbol. A matrix of surviving branch data is stored in an array of registers. Operating the system includes initiating a first traceback from a storage register at a first symbol instant. The traceback traces a path back through the trellis a first predetermined number of symbol instants to determine a first decoded symbol. The length of the traceback is changed and another traceback is executed. This process is repeated until all remaining final decoded symbols are decoded. In an alternate embodiment, the traceback length is repreatedly decremented by one less than the constraint length, with each traceback obtaining multiple decoded symbols.

Abstract: Convolutionally encoded information subjected to channel intersymbol interference is decoded by calculating the minimum cost path through a trellis. The trellis terminates in known states. Exploiting the open architecture of the coprocessor, the minimum cost state is checked to ascertain if it is the known, that is, correct state and if it is not, the possible known states are searched by the DSP inside the ECCP active register and the state with the lowest cost amont the possible states is selected.

Abstract: A digital communication system including a Viterbi decoder for tracing a path through a trellis of individual state information and method of operation are disclosed. The traceback determines a decoded symbol. A trellis of branch origin data is stored in an array of registers. The branch origin data associated with a symbol instant is a cell. Each cell of data is generated by execution of an update instruction form a digital signal process (DSP) to the coprocessor. A first predetermined traceback length is written to a traceback length register. The first predetermined traceback length is small to minimize tracebacks cycling into branch origin data from a previous transmission burst. A traceback is initiated by the DSP providing the coprocessor a single traceback instruction. The Viterbi decoder alternates between update and traceback instructions. At a predetermined symbol instant, the traceback length is increased to a second predetermined length by over-writing the traceback length register.

Abstract: There is disclosed a soft symbol for use in a decoding process generated from a binary representation of a branch metric. When a hard decision bit is a zero, a preselected number of bits of a binary representation of the branch metric are concatenated with a hard decision bit to form the soft symbol. When the hard decision bit is a one, the ones complement of the preselected number of bits of the binary representation of the branch metric are concatenated with the hard decision bit to form the soft symbol. The concatenation function can be achieved using an exclusive OR function with the preselected bits of the binary representation of the branch metric and the hard decision bit to form the soft symbol. The hard decision bit may be selectable from more than one source.