Abstract: An integrated circuit includes a photodetection region configured to receive incident photons. The photodetection region is configured to produce a plurality of charge carriers in response to the incident photons. The integrated circuit includes at least one charge carrier storage region. The integrated circuit also includes a charge carrier segregation structure configured to selectively direct charge carriers of the plurality of charge carriers directly into the at least one charge carrier storage region based upon times at which the charge carriers are produced.

Abstract: An integrated circuit includes a photodetection region configured to receive incident photons. The photodetection region is configured to produce a plurality of charge carriers in response to the incident photons. The integrated circuit also includes at least one charge carrier storage region. The integrated circuit also includes a charge carrier segregation structure configured to selectively direct charge carriers of the plurality of charge carriers into the at least one charge carrier storage region based upon times at which the charge carriers are produced.

Abstract: An integrated circuit includes a photodetection region configured to receive incident photons. The photodetection region is configured to produce a plurality of charge carriers in response to the incident photons. The integrated circuit also includes at least one charge carrier storage region. The integrated circuit also includes a charge carrier segregation structure configured to selectively direct charge carriers of the plurality of charge carriers into the at least one charge carrier storage region based upon times at which the charge carriers are produced.

Abstract: An integrated circuit includes a photodetection region configured to receive incident photons. The photodetection region is configured to produce a plurality of charge carriers in response to the incident photons. The integrated circuit includes at least one charge carrier storage region. The integrated circuit also includes a charge carrier segregation structure configured to selectively direct charge carriers of the plurality of charge carriers directly into the at least one charge carrier storage region based upon times at which the charge carriers are produced.

Abstract: A method of luminance lifetime imaging includes receiving incident photons at an integrated photodetector from luminescent molecules. The incident photons being received through one or more optical components of a point-of-care device. The method also includes detecting arrival times of the incident photons using the integrated photodetector. A method of analyzing blood glucose includes detecting luminance lifetime characteristics of tissue using, at least in part, an integrated circuit that detects arrival times of incident photons from the tissue. The method also includes analyzing blood glucose based upon the luminance lifetime characteristics.

Abstract: An integrated circuit includes a photodetection region configured to receive incident photons. The photodetection region is configured to produce a plurality of charge carriers in response to the incident photons. The integrated circuit also includes at least one charge carrier storage region. The integrated circuit also includes a charge carrier segregation structure configured to selectively direct charge carriers of the plurality of charge carriers into the at least one charge carrier storage region based upon times at which the charge carriers are produced.

Abstract: An integrated circuit includes a photodetection region configured to receive incident photons. The photodetection region is configured to produce a plurality of charge carriers in response to the incident photons. The integrated circuit includes at least one charge carrier storage region. The integrated circuit also includes a charge carrier segregation structure configured to selectively direct charge carriers of the plurality of charge carriers directly into the at least one charge carrier storage region based upon times at which the charge carriers are produced.

Abstract: An integrated circuit includes a photodetection region configured to receive incident photons. The photodetection region is configured to produce a plurality of charge carriers in response to the incident photons. The integrated circuit also includes at least one charge carrier storage region. The integrated circuit also includes a charge carrier segregation structure configured to selectively direct charge carriers of the plurality of charge carriers into the at least one charge carrier storage region based upon times at which the charge carriers are produced.

Abstract: An integrated circuit includes a photodetection region configured to receive incident photons. The photodetection region is configured to produce a plurality of charge carriers in response to the incident photons. The integrated circuit includes at least one charge carrier storage region. The integrated circuit also includes a charge carrier segregation structure configured to selectively direct charge carriers of the plurality of charge carriers directly into the at least one charge carrier storage region based upon times at which the charge carriers are produced.

Abstract: An integrated circuit includes a photodetection region configured to receive incident photons. The photodetection region is configured to produce a plurality of charge carriers in response to the incident photons. The integrated circuit includes at least one charge carrier storage region. The integrated circuit also includes a charge carrier segregation structure configured to selectively direct charge carriers of the plurality of charge carriers directly into the at least one charge carrier storage region based upon times at which the charge carriers are produced.

Abstract: An integrated circuit includes a photodetection region configured to receive incident photons. The photodetection region is configured to produce a plurality of charge carriers in response to the incident photons. The integrated circuit also includes at least one charge carrier storage region. The integrated circuit also includes a charge carrier segregation structure configured to selectively direct charge carriers of the plurality of charge carriers into the at least one charge carrier storage region based upon times at which the charge carriers are produced.

Abstract: A method of luminance lifetime imaging includes receiving incident photons at an integrated photodetector from luminescent molecules. The incident photons being received through one or more optical components of a point-of-care device. The method also includes detecting arrival times of the incident photons using the integrated photodetector. A method of analyzing blood glucose includes detecting luminance lifetime characteristics of tissue using, at least in part, an integrated circuit that detects arrival times of incident photons from the tissue. The method also includes analyzing blood glucose based upon the luminance lifetime characteristics.

Abstract: A linear pixel-array processing systems uses a combination of digital and analog signal processing techniques to calibrate the gain and offset of each pixel in the analog domain. A plurality of fixed gain and offset values are applied in the analog domain to adjust the gain and offset of each pixel at high speeds (on the order of 25–50 MHz). By adjusting the gain and offset in the analog domain, the dynamic range of pixel conversion is improved such that the conversion range is fully utilized (over 90%, on the order of 95%–99%). The gain and offset values are determined with an algorithmic calibration routine that corrects for non-ideal effects in the signal path. A single processing channel can be multiplexed to process multiple pixel arrays to provide for a cost effective solution. In higher speed systems, the single processing channel can be extended to multiple processing channels for improved throughput.

Abstract: A correlated double sampler (CDS) circuit having a ping/pong architecture which employs only a single amplifier, and a CCD image sensor output processing circuit including such a CDS circuit and preferably also an analog-to-digital converter for processing the output of the CDS circuit and a black level correction feedback loop. In one cycle of operation (during processing of the raw output of a CCD sensor), the CDS circuit receives a first set of control signals followed by a second set of control signals, its output signal in response to the first set is indicative of the value of one pixel of a sensed image, and its output signal in response to the second set is indicative of the value of the next pixel of the image. Preferably, each set of control signals consists of a clamp signal, a sample signal, and a hold signal.

Abstract: A structure and a method are provided to receive a high-impedance reference voltage signal and generate a desired output signal that is capable of sourcing enough current to meet the demands of a fixed-resistance load. In such a circuit, the signal from an accurate, wide output-swing voltage source circuit having low quiescent current is combined with the output of a current source circuit so that the voltage input to the load is maintained even as the necessary current is supplied. The current source circuit preferably includes a tracking resistance that sinks a control current which a current mirror multiplies by the same ratio as that between the tracking resistance and the load resistance.

Abstract: There are disclosed electronic imaging systems employing CCD imaging units and one or more unique analog signal processors (ASP's). Each ASP receives color-component image signals from the CCD unit and provides respective output image signals, such as red, green and blue color components, having proper white balance for combining into a full color image. The dark background or zero level of the output image signals is referenced to a common "dark" reference voltage to minimize dark background variations in the combined color image regardless of the gain setting of the ASP or ASP's. Each ASP is substantially identical and has a unique architecture which facilitates its implementation as an integrated circuit. The ASP has a dynamic range of substantially better than 8-bits and provides for a wide range of signal sample rates (e.g., 1 to 40 MHz).

Abstract: An electronic imaging system employes a linear charge coupled device (CCD) imaging unit and a unique analog signal processor (ASP) implemented on a single integrated circuit chip. The ASP has a plurality of matched signal channels for receiving respective pixel image signals from the CCD unit and for providing respective color-component image signals, such as red, green and blue color-components, having amplitude balance and accurately referenced "zero" levels. The ASP also has a plurality of matched multiplexing units which directly combine the separate color-component signals from the signal channels into a single full color output image signal with the color components in timed sequence. The output signal from the ASP is applied to an analog to digital (A/D) converter and then to a digital signal processor (DSP). By virtue of its unique design, the ASP has a dynamic range of greater than 12-bits with an output signal frequency as high as 20 MHz for high throughput rates.

Abstract: There is disclosed an electronic imaging system employing a high efficiency CCD imaging unit and a plurality of unique analog signal processors (ASP's). The ASP's operate in unison for receiving a first color sequence, such as cyan (C), yellow (Y), and green (G), of color-component pixel image signals from the CCD unit and for providing respective output image signals of a second sequence of color components such as blue (B), red (R), and green (G), having proper white balance for combining into a high definition full color image. The dark background or zero level of the output image signals is referenced to a common "dark" reference voltage to minimize dark background variations in the combined color image. Each ASP is substantially identical and has a unique architecture which facilitates its implementation as an integrated circuit. The ASP has a dynamic range of substantially better than 8-bits and provides for a wide range of signal sample rates (e.g., 1 to 40 MHz).

Abstract: A high-gain, low-noise transistor amplifier comprises an input, an output, and first and second field effect transistors each having a gate, a drain, and a source and being formed in a common semiconductor substrate. The second transistor is a depletion mode transistor if it is of the same conductivity type as the first but is an enhancement mode transistor if it is of opposite conductivity type with respect to the first. In an amplifier configuration, the input is coupled to the gate of the first transistor, the source of the first transistor is coupled to the gate of the second transistor, the source of the second transistor is coupled to the output, and there is a direct-coupled feedback path from the source of the second transistor to the drain of the first transistor. At least the first transistor is formed in an isolated well of conductivity opposite to that of the substrate in the semiconductor substrate and its source is coupled directly to that well.

Abstract: In interline transfer type are image sensor wherein photogenerated charge is transferred from a pixel into a charge coupled dvice (CCD) or shift register. The CCD structure is typically composed of two or more overlapping levels of polysilicon electrodes associated with each row of pixels. In accordance with invention, a CCD with simplified structure and hence improved manufacturability is described. The CCD utilizes ion implanted barrier regions, which may be self-aligned such as described by Losee et al. U.S. Pat. No. 4,613,402, to produce a device with single polysilicon electrode associated with each pixel.