Abstract: Methods and apparatus for synchronizing data transfers across clock domains for using heads-up indications. An integrated circuit includes a first-in first-out buffer (FIFO); a memory controller configured to operate in a first clock domain and coupled to the FIFO, the first clock domain associated with a first clock signal; a data fabric configured to operate in a second clock domain and coupled to the FIFO, the second clock domain associated with a second clock signal, a second frequency of the second clock signal being different from a first frequency of the first clock signal; and a controller coupled to the FIFO. In some instances, the controller determines a phase relationship between the first clock signal and the second clock signal; monitors one or more first clock edges of the first clock signal and one or more second clock edges of the second clock signal; and sends a first heads-up signal to the memory controller.

Abstract: Techniques for implementing an overstress design for verification that reduce production and verification time by enabling a verification system to perform verification of components of a circuit design selectively, accurately, and exhaustively under extreme stress scenarios are disclosed. Circuit nodes in an emulation model are selected and overstress is provided to the nodes such that behavior of the circuit under such extreme stress scenarios is readily observable, enabling designers to produce circuits that are more secure, reliable, and resilient in case of failures. Overstress is provided to the node to enable verification of the emulation model without having to design complex test signal representations to produce extreme stress conditions. A request for manufacture is generated including aspects of the emulation model to enable verification of a fabricated circuit in a similar or identical manner to those used to verify the emulation model.

Abstract: Methods and apparatus employ an asynchronous first-in-first-out buffer (FIFO), that includes a plurality of entries. Control logic determines a timing separation between a write header valid signal and corresponding write data valid signal for a write operation to an entry in the first-in-first-out buffer (FIFO) and performs a read of the corresponding data from the entry in the FIFO in the second clock domain, based on the determined timing separation of the write header valid signal and corresponding write data valid signal, and based on a clock frequency ratio between the first and second clock domains.

Abstract: A method and apparatus for synchronizing a time stamp counter (TSC) associated with a processor core in a computer system includes initializing the TSC associated with the processor core by synchronizing the TSC associated with the processor core with at least one other TSC in a hierarchy of TSCs. One or more processor cores are powered down. Upon powering up of the one or more processor cores, the TSC associated with the processor core is synchronized with the at least one other TSC in the hierarchy of TSCs.

Abstract: Methods and apparatus for synchronizing data transfers across clock domains for using heads-up indications. An integrated circuit includes a first-in first-out buffer (FIFO); a memory controller configured to operate in a first clock domain and coupled to the FIFO, the first clock domain associated with a first clock signal; a data fabric configured to operate in a second clock domain and coupled to the FIFO, the second clock domain associated with a second clock signal, a second frequency of the second clock signal being different from a first frequency of the first clock signal; and a controller coupled to the FIFO. In some instances, the controller determines a phase relationship between the first clock signal and the second clock signal; monitors one or more first clock edges of the first clock signal and one or more second clock edges of the second clock signal; and sends a first heads-up signal to the memory controller.

Abstract: A method and apparatus for synchronizing a time stamp counter (TSC) associated with a processor core in a computer system includes initializing the TSC associated with the processor core by synchronizing the TSC associated with the processor core with at least one other TSC in a hierarchy of TSCs. One or more processor cores are powered down. Upon powering up of the one or more processor cores, the TSC associated with the processor core is synchronized with the at least one other TSC in the hierarchy of TSCs.

Abstract: A processor applies offset values to read and write pointers to a first-in-first-out buffer (FIFO) for data being transferred between clock domains. The pointer offsets are based on a frequency ratio between the clock domains, and reduce latency while ensuring that data is not read by the receiving clock domain from an entry of the FIFO until after the data has been written to the entry, thereby reducing data transfer errors. The processor resets the pointer offset values in response to a change in clock frequency at one or both of the clock domains, allowing the processor to continue to accurately transfer data in response to clock frequency changes.

Abstract: A processor applies offset values to read and write pointers to a first-in-first-out buffer (FIFO) for data being transferred between clock domains. The pointer offsets are based on a frequency ratio between the clock domains, and reduce latency while ensuring that data is not read by the receiving clock domain from an entry of the FIFO until after the data has been written to the entry, thereby reducing data transfer errors. The processor resets the pointer offset values in response to a change in clock frequency at one or both of the clock domains, allowing the processor to continue to accurately transfer data in response to clock frequency changes.