Abstract: A method for authenticating features reported by a vehicle includes receiving, from a network, a map of an area with confidence weights corresponding to each feature on the map and/or a list of trusted users; upon the vehicle entering the area, checking whether the vehicle is on the list of trusted users; and checking features reported from the vehicle and matching the features to the map of the area.

Abstract: Various aspects disclosed relate to structure such as a textile, a garment, a garment component, footwear, or a footwear component. The present disclosure includes the structure having a first region having one of more first fibers. An individual first fiber includes co-extruded first and second filaments, the first filament formed of a first thermoplastic polymeric material. Due to expansion or contraction of the one or more first fibers, the first region contracts or expands on a change in relative humidity, relative to an equilibrium state of the first region prior to the change in relative humidity.

Abstract: The present invention discloses a pollution carrying waste treatment apparatus. The disclosed apparatus consists of a pollution carrying tube connected to the treatment cylinder through an elbow for forcing the pollution into the treatment cylinder for treating it with mist sprayer and allowing the treated water to run through water filters to separate contaminated water and re-use the pure water for further processing.

Abstract: An electronic circuit includes an illustrative low voltage CMOS power on reset circuit. The electronic circuit can comprise a power on reset circuit coupled between a supply voltage terminal and a signal node. The illustrative power on reset circuit comprises a voltage detector coupled to the supply voltage terminal which is configured to track CMOS thresholds and deactivate when supply voltage reaches a level for proper operation of CMOS logic.

Abstract: An electronic circuit includes an illustrative low voltage CMOS power on reset circuit. The electronic circuit can comprise a power on reset circuit coupled between a supply voltage terminal and a signal node. The illustrative power on reset circuit comprises a voltage detector coupled to the supply voltage terminal which is configured to track CMOS thresholds and deactivate when supply voltage reaches a level for proper operation of CMOS logic.

Abstract: A disclosed RF circuit includes a power amplifier that produces an RF output signal, a detector to generate a detector signal indicative of a power of the RF output signal, and an offset unit to produce an offset signal that indicates low supply voltage conditions. The power of the RF output signal is reduced, at least in part, by a control signal reflecting a combination of the detector signal and the offset signal. The circuit may include a transmitter to provide an RF input signal to the power amplifier. The transmitter may receive the control signal and adjust a power of the RF input signal based on the control signal. The detector may produce a control current indicative of the RF output signal power. The offset unit produces the offset signal based on a difference between the supply voltage and a nominal supply voltage value.

Abstract: A power amplifier for use in a radio frequency (RF) transmitter or other device exhibits improved protection from voltage standing wave ratio (VSWR) issues emanating from avalanche currents. The amplifier circuit includes a power transistor having a base terminal, and a mirror transistor having a collector terminal and a base terminal. The base terminal is coupled to the collector terminal of the mirror transistor to thereby provide a bias current to the base terminal of the mirror transistor. The base terminal is also coupled to the base terminal of the power transistor to thereby form a base bias feed node for a current mirror arrangement. A static or variable impedance is coupled to the base bias feed node to sink current and to thereby maintain the proper bias current at the base terminal of the mirror transistor to thereby continue operation of the mirror transistor while avalanche conditions exist.

Abstract: Systems and methods are described for improving the startup linearization of a power amplifier. A bias network is provided to generate a bias signal during amplifier startup, and the amplifier is configured to produce an output signal in response to the input signal and the bias signal. A variable impedance is provided to couple the input signal and the output signal in parallel with the amplifier. A controller is configured to apply a weighting function to the variable impedance over at least a startup phase of the amplifier system. By applying a non-linear or other weighting function to the variable impedance during startup, the gain of the amplifier can be controlled to thereby extend a time period over which the output power of the amplifier increases in a generally linear manner toward an operating level.

Abstract: A power amplifier for use in a radio frequency (RF) transmitter or other device exhibits improved protection from voltage standing wave ratio (VSWR) issues emanating from avalanche currents. The amplifier circuit includes a power transistor having a base terminal, and a mirror transistor having a collector terminal and a base terminal. The base terminal is coupled to the collector terminal of the mirror transistor to thereby provide a bias current to the base terminal of the mirror transistor. The base terminal is also coupled to the base terminal of the power transistor to thereby form a base bias feed node for a current mirror arrangement. A static or variable impedance is coupled to the base bias feed node to sink current and to thereby maintain the proper bias current at the base terminal of the mirror transistor to thereby continue operation of the mirror transistor while avalanche conditions exist.

Abstract: Systems and methods are described for improving the startup linearization of a power amplifier. A bias network is provided to generate a bias signal during amplifier startup, and the amplifier is configured to produce an output signal in response to the input signal and the bias signal. A variable impedance is provided to couple the input signal and the output signal in parallel with the amplifier. A controller is configured to apply a weighting function to the variable impedance over at least a startup phase of the amplifier system. By applying a non-linear or other weighting function to the variable impedance during startup, the gain of the amplifier can be controlled to thereby extend a time period over which the output power of the amplifier increases in a generally linear manner toward an operating level.

Abstract: An RF transmitting device (10) includes an RF amplifier (22) formed having components formed on a common semiconductor substrate (14). RF amplifier (22) includes MOS transistors (42) and (44) and an RF choke (46) stacked between a ground node (32) and a Vdd node (36). Transistors (42) and (44) are directly connected together and are biased by a control terminal bias network (58) so that the voltages appearing across their conduction terminals are about equal. Control terminals (56) and (62) of transistors (42) and (44) are driven by in-phase versions of an RF input signal (20).

Abstract: An RF transmitting device (10) includes an RF amplifier (22) formed having components formed on a common semiconductor substrate (14). RF amplifier (22) includes MOS transistors (42) and (44) and an RF choke (46) stacked between a ground node (32) and a Vdd node (36). Transistors (42) and (44) are directly connected together and are biased by a control terminal bias network (58) so that the voltages appearing across their conduction terminals are about equal. Control terminals (56) and (62) of transistors (42) and (44) are driven by in-phase versions of an RF input signal (20).

Abstract: A disclosed RF circuit includes a power amplifier that produces an RF output signal, a detector to generate a detector signal indicative of a power of the RF output signal, and an offset unit to produce an offset signal that indicates low supply voltage conditions. The power of the RF output signal is reduced, at least in part, by a control signal reflecting a combination of the detector signal and the offset signal. The circuit may include a transmitter to provide an RF input signal to the power amplifier. The transmitter may receive the control signal and adjust a power of the RF input signal based on the control signal. The detector may produce a control current indicative of the RF output signal power. The offset unit produces the offset signal based on a difference between the supply voltage and a nominal supply voltage value.

Abstract: A PLL (225) includes a phase detector (202) and a charge pump (210 or 212). The phase detector (202) includes a first D-type flip flop (302), a second D-type flip flop (304) and an AND gate forming a reset circuit (306). The charge pump (210 or 212) includes an up current source (308) and a down current source (310). The up current source (308) provides a constant current. The down current source (310) varies responsive to an output signal (207) generated by the second D-type flip flop (304). The constant current provided by the up current source (308) is made to be less than one half the current provided by the down current source (310) to bias the charge pump (210 or 212) in a negative direction to minimize false locks between the phase of a divided reference frequency signal (206) and the phase of a divided voltage controlled oscillator frequency signal (209).

Abstract: A mid supply reference generator (100, 200, 300) has a first resistance element (106, 206) coupled to a first supply. A second resistance element (108, 208) is coupled to a second supply. A third resistance element (110, 210) is coupled to the second supply A first transistor element (116, 216) is coupled to the first resistance element and the second resistance element, the first transistor element coupled between the first and second resistance element such that the first and second resistance elements provide a reference voltage drop from the same current level. A second transistor element is (120, 220) coupled between the first supply and the mid supply output, the second transistor element to drive the output providing a desired mid supply potential. A third transistor element (118,218) is coupled to the mid supply output and to the third resistance element, the third transistor element and the first transistor element being connected such that they generate proportional currents.

Abstract: A clock driver circuit (100) comprises an input (102) for a reference clock signal. A filter (106) is connected to the input to receive the reference signal and output a filtered signal. A complementary FET driver circuit (108) having a cross-over threshold is coupled to the filter to receive the filtered signal and output a conditioned clock signal.

Abstract: An operational amplifier includes a differential amplifier including a first transistor (120) and a second transistor (122), a gain stage (125), a first folded cascode stage (104) and a second folded cascode stage 106, and a first telescopic stage (108) and a second telescopic stage (110). The folded cascode stages respond to current in the differential amplifier to control the output signal, and the telescopic stages respond to a differential voltage produced by the gain stage to control the output signal.

Abstract: A system (100 or 200) includes a first AGC stage (102) having a programming input and a gain input. A second AGC stage (104 or 210 and 234) is coupled in a common path with the first AGC stage, the second AGC stage having a programming input and a gain input. The first and second AGC stages are programmed by respective programming signals to produce independent gain characteristics responsive to a common gain signal at their respective gain inputs.

Abstract: A communication device (100) employs a local oscillator (104) having an improved charge pump circuit (122). The charge pump circuit (122) has current mirrors (204, 208) in which a first transistor (224, 270) is biased to provide a substantially constant current. A resistor (226, 272) selectively conducts a reference current to bias a mirror transistor (228, 274). The current mirror (204, 208) provides improved dynamic performance thereby reducing global phase error of the communication device (100).

Abstract: A low side line driver (10) includes a slew rate limiter (12) providing current to a pre-charge reference circuit (16). The pre-charge reference circuit (16) generates a constant voltage at the input of a pre-drive circuit (18). Upon a transition to the active state, the pre-charge reference circuit (16) is disabled and current from the slew rate limiter (12) flows to pre-drive circuit (18) which becomes enabled without undue propagation delay or high instantaneous slew rate due to the pre-charge voltage generated by the pre-charge reference circuit (16) before turn on. The pre-drive circuit (18) provides base current to an output driver (22) from a negative voltage created in a charge pump (28). At turn off, an active turn off circuit (26) produces a short output pulse causing rapid discharge of base capacitance of the output driver (22) in order to minimize turn off propagation delay.