Abstract: In a conventional ROM-based digital filtering methodology, N past samples of M-bit input symbols are used to address a memory containing a desired filtered output signal. This memory must have an address space of 2.sup.M*N. According to the present invention, a desired filtered output signal is defined as a composition of signal terms, each of which is a function of less than M*N bits. Individual ROMs are provided for each of these component terms. Address bits for the ROMs are derived from the N past samples of the M-bit input symbols. The ROM outputs are combined to yield the desired filtered output signal.

Abstract: Signal generating apparatus including a phase-locked loop (PLL) utilizing a voltage-controlled oscillator (VCO) and a frequency-locked loop (FLL) to generate an output signal whose frequency jumps from one value to another in a selectable sequence. The signal generator further includes a delay line discriminator to provide an error signal to compensate for FM noise in the VCO. The frequency-locked loop is implemented by utilizing the FM error signal from the delay line discriminator to stabilize the center frequency of the VCO. The inherent wide bandwidth of the FLL provides a fast settling time when the loop is switched to a new frequency. In a learn mode, the gain parameters of the loop are determined and stored each of a plurality of frequencies. The gain parameters and a corresponding pretune signal for each selected frequencies are the applied to the FLL in a selectable sequence to provide a fast-switching signal generator.