Abstract: A serial pixel neighborhood processor serially receives successive rows of pixels at a 10 MHz rate, and operates on three digit by three digit pixel "neighborhoods" to serially output filtered pixels at the 10 MHz rate. The processor includes first through sixth 16 kilobit memories. Odd numbered rows of pixels are serially written into the first memory and even numbered rows of pixels are serially written into the fourth memory. Odd numbered rows of pixels in the first and second memories are serially shifted into the second and third memories, respectively, while even numbered rows of pixels are being written into the fourth memory. Similarly, even numbered rows of pixels in the fourth and fifth memories are serially shifted into the fifth and sixth memories, respectively, while odd numbered rows of pixels are being written into the first memory. The outputs of all of the memories are multiplexed into three bit serial to parallel converters.