Abstract: A controller for use with a magnetic tape drive which has a plurality of buffer memories for temporarily storing data that is passed between the tape drive and a host computer system. Temporary storage of data within the tape controller allows data to be rewritten on the tape if the initial writing is faulty and allows data read from the tape to be reconstructed if the data has been erroneously recorded.Transfer of information into and out of the buffer circuits is controlled by two independent direct memory access circuits--one circuit transfers data between the host computer system and the buffer memories and the other circuit transfer data between the buffer memories and the tape drive. Each of the direct memory access circuits operates independently of the other, however, both circuits are coordinated by a central processing unit which communicates with the direct memory access units by means of an interrupt arrangement.

Abstract: Controller circuitry for a serially-recording magnetic tape drive which is capable of correcting writing errors by rewriting the portions of the data which have been erroneously recorded. Write circuitry in the controller breaks a conventional data record up into one or more blockettes, each of which is assigned a unique sequential blockette number which is recorded on the tape along with the data. After each blockette has been serially recorded sequentially by blockette number on the tape, it is immediately read to check whether it has been properly recorded on the tape. If the blockette has been recorded improperly, the read process directs the write circuitry to rerecord the blockette information at the tape position then under the write head. The recorded blockettes may be out of sequential order since the rerecorded blockette may be located several blockettes after its initial erroneous writing. The data is placed back in sequential order by the read process.

Abstract: Apparatus is disclosed for reading phase encoded digital data from a nine-track magnetic tape which apparatus includes timing circuitry for deriving a clock signal from the recorded data. A portion of the timing circuitry is associated with each track on the tape and automatically accommodates, without generating errors, phase changes in the derived clock signal in that track caused by speed variations in the magnetic tape transport and due to bit shifts caused by certain data patterns.Tape transport speed variations are sensed and the derived clock rate is corrected by a digital phase-locked loop which uses a counter that is clocked at a constant rate to determine the timing "window" during which the circuitry looks for signal transitions on the magnetic tape. A running average of the count remaining in the counter at the time when a transition actually occurs is used to adjust the counter starting value until equilibrium is established.