Abstract: According to one general aspect, a method may include requesting, from a second tier of a cache memory system, a first instruction stored at a first memory address. The method may also include requesting, from a second tier of a branch target buffer system, a branch record associated with the first memory address. The method may also include receiving the branch record before receiving the first instruction. The method may also include pre-fetching, in response to receiving the branch record and before receiving the first instruction, a non-sequential instruction stored at a non-sequential memory address.

Abstract: Less-expensive, faster graphics display can be achieved by an in-parallel scan-line rendering system using a content-searchable memory based on a modified DRAM requiring periodic refresh that includes logical operation circuitry within the refresh circuitry. Data at individual storage locations of the DRAM are periodically read by a refresh amplifier, then a logical operation is performed on the refresh data before application to the write amplifier, allowing searching by data compare and mathematical operations. The data words of the content-searchable memory are loaded with data defining the multi-axis location of each of the vertices of a polygonal facet of an object in the scene and display information concerning the facet, such as color or texture. Data representing out-of-view objects can be culled, and the remaining objects projected onto a viewport, all through in-parallel manipulations in the content-searchable memory.