Abstract: A virtual channel (VC) allocation system is provided. During operation, the system can maintain, at an ingress port of a switch, a set of counters. A respective counter can indicate a number of data units queued at a corresponding egress port for an ingress VC. A data unit can indicate a minimum number of bits needed to form a packet. The system can maintain, at an egress port, an ingress VC indicator indicating that a packet in an egress buffer for an egress VC corresponds to the ingress VC. Upon sending the packet, the system can update a counter based on the ingress VC indicator. The counter can be associated with the egress buffer and the ingress VC. The system can then issue, to a sender device, credits associated with the ingress VC based on a minimum number of available data units indicated by the set of counters.

Abstract: A virtual channel (VC) allocation system is provided. During operation, the system can maintain, at an ingress port of a switch, a set of counters. A respective counter can indicate a number of data units queued at a corresponding egress port for an ingress VC. A data unit can indicate a minimum number of bits needed to form a packet. The system can maintain, at an egress port, an ingress VC indicator indicating that a packet in an egress buffer for an egress VC corresponds to the ingress VC. Upon sending the packet, the system can update a counter based on the ingress VC indicator. The counter can be associated with the egress buffer and the ingress VC. The system can then issue, to a sender device, credits associated with the ingress VC based on a minimum number of available data units indicated by the set of counters.

Abstract: A rework re-timer with forward error correction handling is disclosed. An example first intermediate transceiver includes a first interface to communicatively couple the first intermediate transceiver with a first computing device, a second interface to communicatively couple the first intermediate transceiver to a second intermediate transceiver configured to be communicatively coupled with a second computing device, an auto-negotiation controller to: terminate a first auto-negotiation with the first computing device before the first auto-negotiation is completed, transmit, to the second transceiver, first capabilities of the first computing device determined during the first auto-negotiation, and perform a second auto-negotiation with the first computing device utilizing the first capabilities of the first computing device and second capabilities of the second computing device received from the second transceiver.

Abstract: A network re-timer with forward error correction handling is disclosed. An example network re-timer includes a first receiver to receive data from a first connected device and to re-time the data to generate re-timed data, a first transmitter to transmit the re-timed data to a second connected device, a first auto-negotiation handler communicatively coupled to the first receiver to control a first forward error correction mode for communications with the first connected device, and a second auto-negotiation handler communicatively coupled to the first transmitter to control a second forward error correction mode for communications with the second connected device, wherein the first forward error correction mode is different than the second forward error correction mode.

Abstract: A network re-timer with forward error correction handling is disclosed. An example network re-timer includes a first receiver to receive data from a first connected device and to re-time the data to generate re-timed data, a first transmitter to transmit the re-timed data to a second connected device, a first auto-negotiation handler communicatively coupled to the first receiver to control a first forward error correction mode for communications with the first connected device, and a second auto-negotiation handler communicatively coupled to the first transmitter to control a second forward error correction mode for communications with the second connected device, wherein the first forward error correction mode is different than the second forward error correction mode.

Abstract: A rework re-timer with forward error correction handling is disclosed. An example first intermediate transceiver includes a first interface to communicatively couple the first intermediate transceiver with a first computing device, a second interface to communicatively couple the first intermediate transceiver to a second intermediate transceiver configured to be communicatively coupled with a second computing device, an auto-negotiation controller to: terminate a first auto-negotiation with the first computing device before the first auto-negotiation is completed, transmit, to the second transceiver, first capabilities of the first computing device determined during the first auto-negotiation, and perform a second auto-negotiation with the first computing device utilizing the first capabilities of the first computing device and second capabilities of the second computing device received from the second transceiver.

Abstract: A network transceiver is disclosed. An example system includes a first networking transceiver including a first port and a second port, the first transceiver configured to: negotiate, for use with the first port, a first data rate, negotiate, for use with the second port, a second data rate that is slower than the first data rate, and a second networking transceiver communicatively coupled with the first networking transceiver to communicatively couple computing devices connected to the first networking transceiver to a multi-lane communication port, the second networking transceiver to negotiate, for the multi-lane communication port, a third data rate for communications between the multi-lane communication port and the second networking transceiver.

Abstract: A network transceiver is disclosed. An example system includes a first networking transceiver including a first port and a second port, the first transceiver configured to: negotiate, for use with the first port, a first data rate, negotiate, for use with the second port, a second data rate that is slower than the first data rate, and a second networking transceiver communicatively coupled with the first networking transceiver to communicatively couple computing devices connected to the first networking transceiver to a multi-lane communication port, the second networking transceiver to negotiate, for the multi-lane communication port, a third data rate for communications between the multi-lane communication port and the second networking transceiver.

Abstract: Disclosed is a power isolation and backup system. When a power fail condition is detected, temporary storage is flushed to an SDRAM. After the flush, interfaces are halted, and power is removed from most of the chip except the SDRAM subsystem. The SDRAM subsystem copies data from an SDRAM to a flash memory. On the way, the data may be encrypted, and/or a data integrity signature calculated. To restore data, the SDRAM subsystem copies data from the flash memory to the SDRAM. On the way, the data being restored may be decrypted, and/or a data integrity signature checked.

Abstract: Disclosed is a method and device for concurrently performing a plurality of data manipulation operations on data being transferred via a Direct Memory Access (DMA) channel managed by a DMA controller/engine. A Control Data Block (CDB) that controls where the data is retrieved from, delivered to, and how the plurality of data manipulation operations are performed may be fetched by the DMA controller. A CDB processor operating within the DMA controller may read the CDB and set up the data reads, data manipulation operations, and data writes in accord with the contents of the CDB. Data may be provided from one or more sources and data/modified data may be delivered to one or more destinations. While data is being channeled through the DMA controller, the DMA controller may concurrently perform a plurality of data manipulation operations on the data, such as, but not limited to: hashing, HMAC, fill pattern, LFSR, EEDP check, EEDP generation, XOR, encryption, and decryption.

Abstract: Disclosed is a power isolation and backup system. When a power fail condition is detected, temporary storage is flushed to an SDRAM. After the flush, interfaces are halted, and power is removed from most of the chip except the SDRAM subsystem. The SDRAM subsystem copies data from an SDRAM to a flash memory. On the way, the data may be encrypted, and/or a data integrity signature calculated. To restore data, the SDRAM subsystem copies data from the flash memory to the SDRAM. On the way, the data being restored may be decrypted, and/or a data integrity signature checked.

Abstract: Disclosed is a method and device for concurrently performing a plurality of data manipulation operations on data being transferred via a Direct Memory Access (DMA) channel managed by a DMA controller/engine. A Control Data Block (CDB) that controls where the data is retrieved from, delivered to, and how the plurality of data manipulation operations are performed may be fetched by the DMA controller. A CDB processor operating within the DMA controller may read the CDB and set up the data reads, data manipulation operations, and data writes in accord with the contents of the CDB. Data may be provided from one or more sources and data/modified data may be delivered to one or more destinations. While data is being channeled through the DMA controller, the DMA controller may concurrently perform a plurality of data manipulation operations on the data, such as, but not limited to: hashing, HMAC, fill pattern, LFSR, EEDP check, EEDP generation, XOR, encryption, and decryption.

Abstract: An apparatus and a computer-implemented method for processing data in a bus system component. The bus system component is configured to operate in one of an endpoint mode and a root complex mode. Responsive to configuring the bus system component to operate in endpoint mode, the data is processed through the bus system component according to an endpoint process. Responsive to configuring the bus system component to operate in root complex mode, the data is transferred through the bus system component according to a root complex mode. In an illustrative example, the bus system component is a peripheral control interconnect express component.

Abstract: A system is disclosed for facilitating operation of a peripheral bus, such as a PCI bus, that operates at multiple clock speeds. The system includes an expansion slot controller that identifies the number of peripheral devices that have been installed in the expansion slots, and further determines whether these devices support high speed operation. The expansion slots transmit a signal indicating the presence of a peripheral device in the slot, and also transmit a signal indicating whether the device is operable at the higher clock frequency. Once the expansion slot controller determines this information, it decides whether operation at the higher frequency is supported by the peripheral devices and by the bus bridge. The expansion slot controller informs each peripheral device of what the operating frequency will be, and transmits a signal to the PCI bus bridge indicating if high frequency operation will be supported.

Abstract: The five component composition consisting essentially of:(1) Water soluble antioxidant vitamin C or ascorbic acid, or any of its forms or derivatives, or mixtures thereof.(2) Oil soluble antioxidant vitamin E or Alpha-tocophorol, or any of its forms or derivatives, or mixtures thereof.(3) The element selenium, or a chemical (or composition) containing it, or mixtures thereof. The most preferred chemical containing selenium is dimethyl selenide and mixtures thereof. The words "dimethyl selenide" here and hereinafter mean dimethyl selenide and/or it's oxidation products, including dimethyl selenoxide.(4) A sulfur amino acid, in any form, or a sulfur peptide, or a sulfur protein, or any of their derivatives, or mixtures thereof. The mixture of methionine and cysteine, which contains as impurities some seleno-methionine and some selenocysteine, is preferred,--the tripeptide glutathione containing cysteine is also preferred.

Abstract: A bounce depression device 29 for a high speed poppet valve 11 in a electronically controlled hydraulically operated unit fuel injector 1 comprises a poppet valve 11 with a central bore 35 and a counter bore 33 having a flat inner end 37 and a annular grove 39 on the other end which receives a retainer ring 41 that holds a plurality of flat washer shaped damping rings 31 in the counter bore 33 to absorb momentum by rattling and bouncing as the poppet valve 11 seats to prevent the poppet valve 11 bouncing off the seats 13 and 15.

Abstract: A method and apparatus for designing a computer system which supports multiple processors of different types. A processor base board is separately connectable to a system board. The processor base board includes a number of connectors for receiving processor boards. The processor boards include a processor and, if necessary, a voltage regulator and voltage level converters. A right angle single edge contact connector is used on a Pentium II board to significantly reduce spacing requirements of adjacent processor boards. A conventional pin grid array type socket is used for a Pentium Pro processor board. A special mapping of bus request signals is disclosed for supporting four Pentium Pro processors or two Pentium II processors without requiring changes to the processor base board.

Abstract: A fuel system valve has a metal valve seat and a metal valve body. The metal valve body has a chamber which contains material which is moveable through the chamber in response to deceleration of the valve body. The forces of the material within the chamber on the valve body during rapid deceleration of the valve body counteract the forces subjected on the valve body in response to contact with the valve seat.