Patents by Inventor David M. Picozzi

David M. Picozzi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10295592
    Abstract: Disclosed is a method wherein selective voltage binning and leakage power screening of integrated circuit (IC) chips are performed. Additionally, pre-test power-optimized bin reassignments are made on a chip-by-chip basis. Specifically, a leakage power measurement of an IC chip selected from a voltage bin can is compared to a bin-specific leakage power screen value of the next slower voltage bin. If the leakage power measurement is higher, the IC chip will be left in the voltage bin to which it is currently assigned. If the leakage power measurement is lower, the IC chip will be reassigned to that next slower voltage bin. These processes can be iteratively repeated until no slower voltage bins are available or the IC chip cannot be reassigned. IC chips can subsequently be tested according to testing parameters, including the minimum test voltages, associated with the voltage bins to which they are finally assigned.
    Type: Grant
    Filed: June 13, 2017
    Date of Patent: May 21, 2019
    Assignee: GLOBAL FOUNDRIES INC.
    Inventors: Igor Arsovski, Jeanne P. Bickford, Paul J. Grzymkowski, Susan K. Lichtensteiger, Robert J. McMahon, Troy J. Perry, David M. Picozzi, Thomas G. Sopchak
  • Publication number: 20170276726
    Abstract: Disclosed is a method wherein selective voltage binning and leakage power screening of integrated circuit (IC) chips are performed. Additionally, pre-test power-optimized bin reassignments are made on a chip-by-chip basis. Specifically, a leakage power measurement of an IC chip selected from a voltage bin can is compared to a bin-specific leakage power screen value of the next slower voltage bin. If the leakage power measurement is higher, the IC chip will be left in the voltage bin to which it is currently assigned. If the leakage power measurement is lower, the IC chip will be reassigned to that next slower voltage bin. These processes can be iteratively repeated until no slower voltage bins are available or the IC chip cannot be reassigned. IC chips can subsequently be tested according to testing parameters, including the minimum test voltages, associated with the voltage bins to which they are finally assigned.
    Type: Application
    Filed: June 13, 2017
    Publication date: September 28, 2017
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Igor Arsovski, Jeanne P. Bickford, Paul J. Grzymkowski, Susan K. Lichtensteiger, Robert J. McMahon, Troy J. Perry, David M. Picozzi, Thomas G. Sopchak
  • Patent number: 9759767
    Abstract: Disclosed is a method wherein selective voltage binning and leakage power screening of integrated circuit (IC) chips are performed. Additionally, pre-test power-optimized bin reassignments are made on a chip-by-chip basis. Specifically, a leakage power measurement of an IC chip selected from a voltage bin can is compared to a bin-specific leakage power screen value of the next slower voltage bin. If the leakage power measurement is higher, the IC chip will be left in the voltage bin to which it is currently assigned. If the leakage power measurement is lower, the IC chip will be reassigned to that next slower voltage bin. These processes can be iteratively repeated until no slower voltage bins are available or the IC chip cannot be reassigned. IC chips can subsequently be tested according to testing parameters, including the minimum test voltages, associated with the voltage bins to which they are finally assigned.
    Type: Grant
    Filed: April 24, 2015
    Date of Patent: September 12, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Igor Arsovski, Jeanne P. Bickford, Paul J. Grzymkowski, Susan K. Lichtensteiger, Robert J. McMahon, Troy J. Perry, David M. Picozzi, Thomas G. Sopchak
  • Publication number: 20160313394
    Abstract: Disclosed is a method wherein selective voltage binning and leakage power screening of integrated circuit (IC) chips are performed. Additionally, pre-test power-optimized bin reassignments are made on a chip-by-chip basis. Specifically, a leakage power measurement of an IC chip selected from a voltage bin can is compared to a bin-specific leakage power screen value of the next slower voltage bin. If the leakage power measurement is higher, the IC chip will be left in the voltage bin to which it is currently assigned. If the leakage power measurement is lower, the IC chip will be reassigned to that next slower voltage bin. These processes can be iteratively repeated until no slower voltage bins are available or the IC chip cannot be reassigned. IC chips can subsequently be tested according to testing parameters, including the minimum test voltages, associated with the voltage bins to which they are finally assigned.
    Type: Application
    Filed: April 24, 2015
    Publication date: October 27, 2016
    Inventors: Igor Arsovski, Jeanne P. Bickford, Paul J. Grzymkowski, Susan K. Lichtensteiger, Robert J. McMahon, Troy J. Perry, David M. Picozzi, Thomas G. Sopchak