Abstract: Systems and methods are provided that may be implemented to identify and track layer changes of an integrated circuit (IC) device, e.g., during any one of circuit design, pattern generation, device fabrication and/or chip failure analysis processes. Multiple revisions and variants of different IC layers may be identified and tracked using a tracking system and standardized labeling scheme that employs a combination of identifier characters and identifier structures that may be further implemented using revision layer identification parameterized cells (layerID PCells and BooleanID PCells) that include such identifier characters and/or structures The disclosed tracking systems may be further implemented in an automated manner and/or in a manner that allows programming of various parts/aspects and layerID PCells and BooleanID PCells of the tracking system.

Abstract: Systems and methods are provided that may be implemented to identify and track layer changes of an integrated circuit (IC) device, e.g., during any one of circuit design, pattern generation, device fabrication and/or chip failure analysis processes. Multiple revisions and variants of different IC layers may be identified and tracked using a tracking system and standardized labeling scheme that employs a combination of identifier characters and identifier structures that may be further implemented using revision layer identification parameterized cells (layerID PCells and BooleanID PCells) that include such identifier characters and/or structures The disclosed tracking systems may be further implemented in an automated manner and/or in a manner that allows programming of various parts/aspects and layerID PCells and BooleanID PCells of the tracking system.

Abstract: A silicide-interface polysilicon resistor is disclosed. The silicide-interface polysilicon resistor includes a substrate, an oxide layer located on top of the substrate, and a polysilicon layer located on top of the oxide layer. The polysilicon layer includes multiple semiconductor junctions. The silicide-interface polysilicon resistor also includes a layer of silicide sheets, and at least one of the silicon sheets is in contact with one of the semiconductor junctions located within the polysilicon layer.

Abstract: A silicide-interface polysilicon resistor is disclosed. The silicide-interface polysilicon resistor includes a substrate, an oxide layer located on top of the substrate, and a polysilicon layer located on top of the oxide layer. The polysilicon layer includes multiple semiconductor junctions. The silicide-interface polysilicon resistor also includes a layer of silicide sheets, and at least one of the silicon sheets is in contact with one of the semiconductor junctions located within the polysilicon layer.

Abstract: An ESD diode protects a circuit against electrostatic discharge (ESD). The ESD diode has four adjacent regions. The first and third regions are formed by doping a semiconductor substrate so that it has a P-type conductivity. The second and fourth regions are formed by doping the semiconductor substrate so that it has an N-type conductivity. The first region is for connection to a signal terminal of the circuit being protected when the fourth region is connected to a positive power line of the circuit. The fourth region is for connection to the signal terminal when the first region is connected to the ground line or a negative power line of the circuit.

Abstract: A lateral bipolar transistor for an intergrated circuit is provided that maintains a high current gain and high frequency capability without sacrificing high Early voltage. More particularly, a lateral bipolar transistor is formed on an integrated circuit having both bipolar and CMOS devices, the lateral bipolar transistor being formed according to the BiCMOS method and without additional steps relative to formation of vertical bipolar devices if provided in the same area. Among other things, an integrated circuit is provided in which P well structures are provided in the collector regions of an LPNP that have been found to affect a significant increase in the product of the Early voltage and the current gain.

Abstract: A bi-directional ESD diode protects a circuit against electrostatic discharge (ESD). The bi-directional diode has a first device and a second device, each including a first region and a third region formed by doping a semiconductor substrate so that it has a P-type conductivity; and a second region and a fourth region formed by doping the semiconductor substrate so that it has an N-type conductivity. The first region of the first device and the fourth region of the second device are for connection to an anode terminal of the bi-directional diode. The fourth region of the first device and the first region of the second device are for connection a cathode terminal of the bi-directional diode. The anode terminal is for connection to a signal terminal of the circuit when the cathode terminal is connected to a positive power line of the circuit, and the cathode terminal is for connection to the signal terminal when the anode terminal is connected to a ground line or a negative power line of the circuit.

Abstract: A lateral bipolar transistor for an intergrated circuit is provided that maintains a high current gain and high frequency capability without sacrificing high Early voltage. More particularly, a lateral bipolar transistor is formed on an integrated circuit having both bipolar and CMOS devices, the lateral bipolar transistor being formed according to the BiCMOS method and without additional steps relative to formation of vertical bipolar devices if provided in the same area. Among other things, an integrated circuit is provided in which P well structures are provided in the collector regions of an LPNP that have been found to affect a significant increase in the product of the Early voltage and the current gain.