Abstract: Interface circuitry for obtaining simultaneous, multi-channel analog outputs from a microprocessor, avoiding sequential addressing delays. The technique involves inserting, for each analog output channel, a buffer latch between the data bus lines from the microprocessor and the D/A latch associated with the D/A converter. The buffer latches are sequentially addressed by control logic circuitry and loaded from the computer memory in accordance with software instructions in the microprocessor. While data is being loaded in the buffer latches, the D/A latches are disabled, preventing the data from being presented to the D/A converters. When all channels are loaded, the D/A latches are strobed simultaneously, enabling them and transferring the data stored in the buffer latches to the D/A converters for conversion to analog outputs.