Patents by Inventor David M. Weber

David M. Weber has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10497204
    Abstract: A method for tracking an event of an externally controlled interface (ECI) is described. The method includes generating the externally controlled interface independent of an outcome of a wager-based game regulated by a regulatory authority, and logging the event of the externally controlled interface.
    Type: Grant
    Filed: May 11, 2016
    Date of Patent: December 3, 2019
    Assignee: IGT
    Inventors: Reid M. Weber, William C. Little, Steven G. LeMay, Adrian R. Marcu, Warner R. Cockerille, IV, Nicole M. Beaulieu, David A. Gipp, Daniel de Waal, Vincent S. Manfredi, Bryan Bullard, Cara L. Iddings, Richard J. Schneider, Glenn Keith Russell, Jacob Graham, Gregory A. Schlottmann, Richard E. Rowe, David C. Williams, Kurt M. Larsen, Jae Man Yi, Erik B. Petersen
  • Publication number: 20190266653
    Abstract: A user interface is described that enables a user to select and visualize different configurations of building products, perform a visual comparison of different configurations, save views of visualizations of the configurations, and obtain building product literature of the materials in the configurations. In some embodiments, the user interface can identify contractors for a user and facilitate communication with the contractors.
    Type: Application
    Filed: February 26, 2019
    Publication date: August 29, 2019
    Inventors: William L. West, David C. Anderson, Mark T. Green, Joshua M. Weber, Nathan B. Creech
  • Publication number: 20190181461
    Abstract: The present disclosure relates membrane-electrode assemblies and electrochemical cells and liquid flow batteries produced therefrom. The membrane-electrode assemblies include a first porous electrode; an ion permeable membrane, having a first major surface and an opposed second major surface; a first discontinuous transport protection layer disposed between the first porous electrode and the first major surface of the ion permeable membrane; and a first adhesive layer in contact with the first porous electrode and at least one of the first discontinuous transport protection layer and the ion permeable membrane. The first adhesive layer is disposed along the perimeter of the membrane-electrode assembly.
    Type: Application
    Filed: August 9, 2017
    Publication date: June 13, 2019
    Inventors: Brian T. Weber, Brandon A. Bartling, Onur Sinan Yordem, Andrew T. Haug, John E. Abulu, Gregory M. Haugen, Kazuki Noda, Shunsuke Suzuki, Bharat R. Acharya, Daniel M. Pierpont, David J. Miller, Eric J. Iverson
  • Patent number: 8168433
    Abstract: A method for producing a cell culture article having a synthetic polymer layer for incubating with cells includes diluting one or more (meth)acrylate monomers in a solvent and dispersing the diluted monomers on a surface of the cell culture article. Some or substantially all of the solvent is removed and the monomers are then polymerized on the surface of the article to form the synthetic polymer layer attached to the surface of the article.
    Type: Grant
    Filed: January 30, 2009
    Date of Patent: May 1, 2012
    Assignee: Corning Incorporated
    Inventors: Jennifer Gehman, Arthur W. Martin, Zara Melkoumian, Christopher B. Shogbon, David M. Weber, Yue Zhou
  • Patent number: 7818461
    Abstract: Systems and methods for allocating assets to a plurality of devices are presented. In one embodiment, devices may be communicatively connected to one another through a device loop. Each device may be configured for determining a portion of an asset that it will use. A controller may also be communicatively connected to the communication medium and configured for determining a capacity of the asset. The controller may transfer control information to the devices so as to allocate the asset to the devices based on the capacity of that asset. In another embodiment, each of the devices may be communicatively connected directly to the controller rather than to one another.
    Type: Grant
    Filed: April 28, 2003
    Date of Patent: October 19, 2010
    Assignee: LSI Corporation
    Inventor: David M. Weber
  • Publication number: 20090203065
    Abstract: A method for producing a cell culture article having a synthetic polymer layer for incubating with cells includes diluting one or more (meth)acrylate monomers in a solvent and dispersing the diluted monomers on a surface of the cell culture article. Some or substantially all of the solvent is removed and the monomers are then polymerized on the surface of the article to form the synthetic polymer layer attached to the surface of the article.
    Type: Application
    Filed: January 30, 2009
    Publication date: August 13, 2009
    Inventors: JENNIFER GEHMAN, ARTHUR W. MARTIN, ZARA MELKOUMIAN, CHRISTOPHER B. SHOGBON, DAVID M. WEBER, YUE ZHOU
  • Publication number: 20040215779
    Abstract: Systems and methods for allocating assets to a plurality of devices are presented. In one embodiment, devices may be communicatively connected to one another through a device loop. Each device may be configured for determining a portion of an asset that it will use. A controller may also be communicatively connected to the communication medium and configured for determining a capacity of the asset. The controller may transfer control information to the devices so as to allocate the asset to the devices based on the capacity of that asset. In another embodiment, each of the devices may be communicatively connected directly to the controller rather than to one another.
    Type: Application
    Filed: April 28, 2003
    Publication date: October 28, 2004
    Inventor: David M. Weber
  • Patent number: 6788091
    Abstract: A mechanism if provided for testing newly-manufactured integrated circuits at the wafer stage. Built-in self-test circuitry is used to test each of the die on a wafer in parallel. Then, when a defect is detected, the die marks itself (e.g., by physically destroying a portion of itself through burnout). The present mechanism eliminates the inefficiencies of serial testing of die and of mechanical latency as each die is positioned for testing.
    Type: Grant
    Filed: November 5, 2001
    Date of Patent: September 7, 2004
    Assignee: LSI Logic Corporation
    Inventor: David M. Weber
  • Publication number: 20040120696
    Abstract: The present invention provides a system and method for utilizing a camcorder as a tape backup device for a computing system. A communicative link is established between a camcorder and a computing system which allows data from the computing system to be communicated to the camcorder. The data, once received by the camcorder, is stored in a storage medium of the camcorder.
    Type: Application
    Filed: December 19, 2002
    Publication date: June 24, 2004
    Inventors: Richard L. Solomon, Steven Callicott, David M. Weber
  • Patent number: 6747984
    Abstract: A method and apparatus for transmitting data in a node having a buffer. A first set of data is received in a buffer for transmission to a target node. The first set of data is sent to the target node. Responsive to an indication that the target node is unable to receive data, a second set of data is loaded into the buffer for transmission to another target node, while the first set of data is retained in the buffer.
    Type: Grant
    Filed: December 18, 1998
    Date of Patent: June 8, 2004
    Assignee: LSI Logic Corporation
    Inventors: Timothy E. Hoglund, Stephen M. Johnson, David M. Weber, John M. Adams, Mark A. Reber
  • Publication number: 20030120791
    Abstract: The present invention is a novel system and method for implementing multiple protocol definitions including multiple interconnect protocols and protocol methods. Protocol methods may include a single-thread, multi-speed interconnect protocol method and a multi-thread, single-speed interconnect protocol method with shared resources on a single die. Various aspects of serializer/deserializer, encoder/decoder, aggregator, and protocol functions may be shared among both protocol definitions to provide cost and real estate efficiency.
    Type: Application
    Filed: December 20, 2001
    Publication date: June 26, 2003
    Inventors: David M. Weber, Silvia E. Jaeckel, Mark Miquelon
  • Patent number: 6570853
    Abstract: A method and apparatus in a source node for transmitting data to a target node. Responsive to a request to transmit data to the target node, a determination is made as to whether a selected period of time has passed without data transmitted from the source node being received by the target node. Responsive to detecting the selected period of time has passed without data transmitted from the source node being received by the target node, a determination is made as to whether space is available in the target node to receive the data. Responsive to a determination that space is unavailable in the target node, generating an indication that the target node is blocked is generated.
    Type: Grant
    Filed: October 4, 2000
    Date of Patent: May 27, 2003
    Assignee: LSI Logic Corporation
    Inventors: Stephen M. Johnson, Timothy E. Hoglund, David M. Weber, John M. Adams, Mark A. Reber
  • Patent number: 6274395
    Abstract: A method of fabricating a semiconductor wafer includes the step of fabricating a number of die on the wafer. The method also includes the step of fabricating a memory device on the wafer. The method further includes the step of testing the number of die with a die testing apparatus so as to obtain test data associated with the number of die. In addition, the method includes the step of storing the test data obtained during the testing step in the memory device. Moreover, the method includes the step of retrieving the test data from the memory device. Yet further, the method includes the step of operating a packaging apparatus so as to package a first die of the number of die based on the test data. A semiconductor wafer is also disclosed.
    Type: Grant
    Filed: December 23, 1999
    Date of Patent: August 14, 2001
    Assignee: LSI Logic Corporation
    Inventor: David M. Weber
  • Patent number: 6246278
    Abstract: A dual-phase clock divider circuit provides the ability to generate high speed complementary clocks with low skew. The dual-phase clock divider circuit runs off a single clock input, such as provided by a high speed VCO. This eliminates the effect of clock skew in the highest speed portion of the circuit. The dual-phase clock divider then generates complementary outputs of low skew to be used by other clocked elements.
    Type: Grant
    Filed: December 22, 1995
    Date of Patent: June 12, 2001
    Assignee: LSI Logic Corporation
    Inventors: Michael B. Anderson, Kenneth C. Schmitt, David M. Weber
  • Patent number: 6185620
    Abstract: A method and apparatus for transferring data from a host to a node through a fabric connecting the host to the node. A chip architecture is provided in which a protocol engine provides for on ship processing in transferring data such that frequent interrupts from various components within the chip may be processed without intervention from the host processor. Additionally, context managers are provided to transmit and receive data. The protocol engine creates a list of transmit activities, which is traversed by the context managers, which in turn execute the listed activity in a fashion independent from the protocol engine. In receiving data, the context managers provide a mechanism to process frames of data originating from various sources without requiring intervention from the protocol engine. When receiving data, the context managers are able to process frames from different sources, which arrive out of order.
    Type: Grant
    Filed: April 3, 1998
    Date of Patent: February 6, 2001
    Assignee: LSI Logic Corporation
    Inventors: David M. Weber, Timothy E. Hoglund, Stephen M. Johnson, John M. Adams, Mark A. Reber
  • Patent number: 6134617
    Abstract: A method and apparatus for transferring data from a host to a node through a fabric connecting the host to the node. A chip architecture is provided in which a protocol engine provides for on chip processing in transferring data such that frequent interrupts from various components within the chip may be processed without intervention from the host processor. Additionally, context managers are provided to transmit and receive data. The protocol engine creates a list of transmit activities, which is traversed by the context managers, which in turn execute the listed activity in a fashion independent from the protocol engine. In receiving data, the context managers provide a mechanism to process frames of data originating from various sources without requiring intervention from the protocol engine. When receiving data, the context managers are able to process frames from different sources, which arrive out of order.
    Type: Grant
    Filed: April 3, 1998
    Date of Patent: October 17, 2000
    Assignee: LSI Logic Corporation
    Inventor: David M. Weber
  • Patent number: 6097775
    Abstract: A method and apparatus of a synchronizer circuit for transferring signals between two clock domains in which a first synchronizer unit and a second synchronizer unit form a hand-shaking protocol. In particular, an input event from a source clock domain is captured in an input unit and a first signal is asserted indicating that the input signal is to be transferred to a target clock domain. This first signal is synchronized to the clock signal in the target clock domain at the first synchronizer unit, causing assertion of a second signal. The second signal is coupled to an output unit which generates an output event signal for a single clock period.
    Type: Grant
    Filed: February 17, 1998
    Date of Patent: August 1, 2000
    Assignee: LSI Logic Corporation
    Inventor: David M. Weber
  • Patent number: 6080571
    Abstract: This invention is directed to a continuous process for producing viral particles comprising providing in a perfused growth medium a population of viable virally infected non-lytic cells, and removing medium containing said cells at a rate to maintain the steady-state log-phase growth of cells remaining in said perfused growth medium. The invention is also directed to a process for purifying retroviral particles comprising passing a solution comprising the retroviral particles and contaminants through an anion exchange resin, and eluting the retroviral particles from the resin.
    Type: Grant
    Filed: April 15, 1997
    Date of Patent: June 27, 2000
    Assignee: The Immune Response Corporation
    Inventors: Christopher P. Prior, David M. Weber, Richard S. Gore, James J. Harter
  • Patent number: 5781769
    Abstract: A method and associated apparatus for using a content addressable memory (CAM) to process timed events in a process control application. A time value field in each CAM entry identifies the time at which a corresponding event is to be processed. An event identifier field in each CAM entry identifies the event to be processed. A time value generator applies signals indicative of a time value to the CAM. The CAM returns as data on its output signal paths any entries whose time value fields correspond to the applied time value signals. The event identifier field applied to the output signal paths of the CAM is then applied to the process controller to identify an event to be processed. The methods and apparatus of the present invention are applicable, for example, in communication controller devices wherein a protocol requires timed event processing for standardized communications (e.g., Fibre Channel or FDDI).
    Type: Grant
    Filed: December 29, 1995
    Date of Patent: July 14, 1998
    Assignee: Symbios, Inc.
    Inventor: David M. Weber
  • Patent number: 5777987
    Abstract: A method and associated apparatus for using a primary FIFO and one or more secondary FIFOs in parallel to simplify flow control and routing in packet communication operations wherein at least one FIFO (buffer) is associated with each of a plurality of receiving nodes or components within a receiving node. The present invention applies received packets simultaneously to a primary FIFO and to all associated secondary FIFOs in the receiver of a packet communications link. After receipt of a packet, the packet is removed from any secondary FIFOs which correspond to receiver nodes or components to which the packet was not routed. For all receiving nodes or components to which the packet was routed, if the packet was stored in each associated secondary FIFO without overflow, then the packet is also purged from the primary FIFO.
    Type: Grant
    Filed: December 29, 1995
    Date of Patent: July 7, 1998
    Assignee: Symbios, Inc.
    Inventors: John M. Adams, Timothy E. Hoglund, Stephen M. Johnson, Mark A. Reber, David M. Weber