Abstract: In embodiments of the present invention a device, circuit, and method are described for sampling input signal voltages, which may include voltages below a negative supply voltage for the device or circuit, without requiring static current from the input. Various embodiments of the invention obviate the requirement of an external negative supply voltage or attenuation resistors to allow sampling between a positive and negative voltage range. These embodiments result in a lower power sampling solution as well as simplifying any driver circuitry required by the sampler. The embodiments of the invention may be applied to sampling processes within analog-to-digital converters and may also be applicable to various other types of circuits in which a sampling input having input voltages that are lower than its negative supply voltage.

Abstract: A system, apparatus and a method are described that provide a voltage clamp for a single-supply system. In particular, a negative voltage clamp prevents a negative over-voltage in a system having only a positive independent voltage source. For example, certain analog-to-digital converters and other circuits allow input signals below the negative supply, or ground in single-supply systems, either by direct sampling or using input attenuation resistors. The negative clamp allows the circuit to provide accurate negative over-voltage protection and the absence of this claim would result in over-voltage protection in positive voltage directions only.

Abstract: In embodiments of the present invention a device, circuit, and method are described for sampling input signal voltages, which may include voltages below a negative supply voltage for the device or circuit, without requiring static current from the input. Various embodiments of the invention obviate the requirement of an external negative supply voltage or attenuation resistors to allow sampling between a positive and negative voltage range. These embodiments result in a lower power sampling solution as well as simplifying any driver circuitry required by the sampler. The embodiments of the invention may be applied to sampling processes within analog-to-digital converters and may also be applicable to various other types of circuits in which a sampling input having input voltages that are lower than its negative supply voltage.

Abstract: In embodiments of the present invention a device, circuit, and method are described for sampling input signal voltages, which may include voltages below a negative supply voltage for the device or circuit, without requiring static current from the input. Various embodiments of the invention obviate the requirement of an external negative supply voltage or attenuation resistors to allow sampling between a positive and negative voltage range. These embodiments result in a lower power sampling solution as well as simplifying any driver circuitry required by the sampler. The embodiments of the invention may be applied to sampling processes within analog-to-digital converters and may also be applicable to various other types of circuits in which a sampling input having input voltages that are lower than its negative supply voltage.

Abstract: In embodiments of the present invention a device, circuit, and method are described for sampling input signal voltages, which may include voltages below a negative supply voltage for the device or circuit, without requiring static current from the input. Various embodiments of the invention obviate the requirement of an external negative supply voltage or attenuation resistors to allow sampling between a positive and negative voltage range. These embodiments result in a lower power sampling solution as well as simplifying any driver circuitry required by the sampler. The embodiments of the invention may be applied to sampling processes within analog-to-digital converters and may also be applicable to various other types of circuits in which a sampling input having input voltages that are lower than its negative supply voltage.

Abstract: A system, apparatus and a method are described that provide a voltage clamp for a single-supply system. In particular, a negative voltage clamp prevents a negative over-voltage in a system having only a positive independent voltage source. For example, certain analog-to-digital converters and other circuits allow input signals below the negative supply, or ground in single-supply systems, either by direct sampling or using input attenuation resistors. The negative clamp allows the circuit to provide accurate negative over-voltage protection and the absence of this claim would result in over-voltage protection in positive voltage directions only.

Abstract: High speed digital path for successive approximation analog-to-digital converters wherein the successive approximation registers and the switch drivers are combined in set-reset latches having the switch drivers as latch outputs. This reduces the time of each successive approximation by reducing the ripple through time of each stage, thereby increasing the speed of operation of the analog-to-digital converters. As an option, the set-reset latches having the switch drivers as latch outputs may also incorporate level shifting to combine each stage of the successive approximation register, associated switch drivers and level shifters into a single circuit for each stage of the analog-to-digital converter. Various embodiments are disclosed.

Abstract: Sample and hold circuits and methods to reduce distortion. A signal to be sampled is connected across a capacitor through a field effect device, which field effect device is turned off when the sample voltage across the capacitor is to be held. When the field effect device coupling the sample voltage to the capacitor is turned on, the body and gate voltages of the field effect device are made to have a fixed voltage relative to the voltage being sampled, so that the characteristics of the field effect device are unaffected by signal variations during sampling or between samples. Exemplary embodiments are disclosed.

Abstract: The present invention provides a switch circuit having a switch and a first body grabbing circuit. The switch includes a first transistor and a second transistor. The first transistor has a body and is coupled to the second transistor in parallel to form a common source and a common drain. The common source defines an input node and the common drain defines an output node. The first body grabbing circuit is coupled to the body of the first transistor. The first body grabbing circuit is arranged to couple the body of the first transistor to the input node when the first and second transistors receive a turn-on voltage signal such that a body effect is eliminated in the first transistor.