Abstract: In the context of electronic design automation and particularly circuit layout design software tools, systems and methods for incremental chaining of circuit devices (or, more generally, “figures,” which can include instances and pins) permit user-interactive abutment and placement. Selection of one or more anchor figures highlights chaining candidates which can be automatically chained to the anchor figure(s) upon selection, as with a single mouse click. As compared to manual interactive abutment or automatic batch-mode chaining, incremental chaining offers improved usability, reduced manual effort, and the opportunity for user interaction as a chain is constructed, because the user is permitted interventions at any point in the chaining process for altering device parameters or characteristics.

Abstract: Disclosed herein are embodiments of systems, methods, and products that generate two dimensional chains of layout devices, by retrieving the schematic orientation of schematic devices in a symbolic view, and abutting the layout devices based on the schematic orientation such that the two dimensional chains of the layout devices maintain the schematic orientation. More specifically, EDA systems and methods disclosed herein may separate the layout devices into different sets, wherein each set may contain a particular type of layout devices. For example, a first set may contain photonic waveguides and a second set may contain radio frequency (RF) transmission lines. For each set of layout devices, the EDA systems and methods deterministically and iteratively traverse through the layout devices, abutting the devices using the schematic orientation, and creating one or more two dimensional chains of the layout devices.

Abstract: Disclosed herein are embodiments of systems, methods, and products using a center access direction for pin figures during an abutment of instances in an integrated circuit (IC) design. Using a center access direction allows an electronic design automation (EDA) tool to overlap the centers of the pin figures to be merged. Once the centers of the pin figures are overlapped, the EDA tool runs one or more merging and optimization algorithms to abut the circuit devices containing the pin figures. The EDA tool therefore is computationally efficient and yet provides more functionality: unlike the conventional system, the EDA tool does not have to align the pin figures and calculate an offset to overlap the pin figures post alignment. Furthermore, the EDA tool can overlap the pin figures from any angle and is not confined to rectilinear access direction of the conventional systems.

Abstract: The present invention provides a method for resolving a circuit connection violation that comprises categorizing a circuit chain with the connection violation into a class, and performing one or more transformation algorithms on the circuit chain from the group consisting of a chain mirror, a cascade mirror, a cascade mirror permute, and a cut chain mirror algorithm based on the class of the circuit chain.

Abstract: A system and method for optimizing a design layout by identifying features for abutment where the shapes that trigger the abutment are overlapping, within a predefined proximity of each other, or are interface elements for features having a short circuit. The abutment process may identify shapes for abutment that are not connected to a netlist of the design or are otherwise not associated with a connection pin. The abutment process may adjust a shape or feature including, for example by resizing, moving, inserting, or removing one or more shapes from the layout in accordance with predefined layout rules. After the shapes and features have been adjusted abutments may be formed between the features.

Abstract: The present invention provides a method for resolving a circuit connection violation that comprises categorizing a circuit chain with the connection violation into a class, and performing one or more transformation algorithms on the circuit chain from the group consisting of a chain mirror, a cascade mirror, a cascade mirror permute, and a cut chain mirror algorithm based on the class of the circuit chain.