Abstract: The technology described herein relates to a method of generating an encoded output video frame for transmission to an electronic display in which an encoded source video frame is decoded to obtain a decoded source video frame 200a, the decoded source video frame 200a is processed to obtain an input video frame 200c, and the input video frame 200c is encoded to obtain an encoded output video frame for transmission.

Abstract: The technology described herein relates to a method of generating an encoded output video frame for transmission to an electronic display in which an encoded source video frame is decoded to obtain a decoded source video frame 200a, the decoded source video frame 200a is processed to obtain an input video frame 200c, and the input video frame 200c is encoded to obtain an encoded output video frame for transmission.

Abstract: A superscalar data processing apparatus and method are provided for processing operations, the apparatus having a plurality of execution threads and each execution thread being operable to process a sequence of operations including at least one memory access operation. The superscalar data processing apparatus comprises a plurality of execution pipelines for executing the operations, and issue logic for allocating each operation to one of the execution pipelines for execution by that execution pipeline. At least two of the execution pipelines are memory access capable pipelines which can execute memory access operations, and each memory access capable pipeline is associated with a subset of the plurality of execution threads. The issue logic is arranged, for each execution thread, to allocate any memory access operations of that execution thread to an associated memory access capable pipeline.

Abstract: A data processing apparatus and method are provided for managing snoop operations. The data processing apparatus comprises a plurality of processing units for executing a number of processes by performing data processing operations requiring access to data in shared memory. Each processing unit has a cache for storing a subset of the data for access by that processing unit, the data processing apparatus employing a snoop-based cache coherency protocol to ensure data access by each processing unit is up-to-date. Each processing unit has a storage element associated therewith identifying snoop control data, whereby when one of the processing units determines that a snoop operation is required having regard to the cache coherency protocol, that processing unit references the snoop control data in its associated storage element in order to determine which of the plurality of processing units are to be subjected to the snoop operation.

Abstract: A system, method and computer program product are provided for testing software to be run on a data processing apparatus having a processor for performing data processing operations, a memory for storing data for access by the processor, and at least one temporary storage located between the processor and the memory and operable to temporarily store data to improve speed of access to that data by the processor. The software tested controls the maintenance of data by the at least one temporary storage. The test system comprises a processor simulator for simulating the data processing operations performed by the processor, including issuing an access request when access to a data value is required, the access request causing one or more data access operations to be performed. The test system also includes a temporary storage simulator provided for each temporary storage, and arranged to simulate the operation of that associated temporary storage.

Abstract: A data processing apparatus and method for generating constant values is provided. The data processing apparatus comprises a data processing unit operable in response to an instruction to perform a data processing operation on one or more data values. Shift logic is operable to selectively apply a shift operation to data to produce one of the data values for the data processing operation. Further, a plurality of registers are provided for storing data. The instruction has a register specifier field for identifying a register and a shift specifier field for specifying a shift to be applied to that register's data in order to produce one of the data values for the data processing operation.

Abstract: The present invention provides a data processing apparatus and method of controlling access to a shared resource. The data processing apparatus has a plurality of processors operable to perform respective data processing operations requiring access to the shared resource, and a path is provided interconnecting the plurality of processors. An access control mechanism is operable to control access to the shared resource by the plurality of processors, each processor being operable to enter a power saving mode if access to the shared resource is required but the access control mechanism is preventing access to the shared resource by that processor. Further, each processor is operable, when that processor has access to the shared resource, to issue a notification on the path when access to the shared resource is no longer required by that processor. A processor in the power saving mode is arranged, upon receipt of that notification, to exit the power saving mode and to seek access to the shared resource.

Abstract: There is provided an apparatus for processing data, said apparatus comprising: a processor operable in a plurality of modes and either a secure domain or a non-secure domain including: at least one secure mode being a mode in said secure domain; and at least one non-secure mode being a mode in said non-secure domain; wherein when said processor is executing a program in a secure mode said program has access to secure data which is not accessible when said processor is operating in a non-secure mode; and a vectored interrupt controller operable to generate an exception handler address for supply to said processor in response to occurrence of an exception condition in accordance with programmable parameters specifying: for each of a plurality of exception conditions, a domain value indicating whether said exception condition should trigger an exception handler in said secure domain or said non-secure domain; for each of said plurality of exception conditions, an exception handler address for use if said excepti

Abstract: A data processing apparatus and method are provided for controlling access to a slave device, the slave device having an address range associated therewith. The apparatus comprises control storage programmable to define a partition identifying a secure region and a non-secure region in the address range, with the data processing apparatus supporting a plurality of modes of operation including a secure mode, and the control storage being programmable only by software executing in the secure mode. A master device is arranged to issue an access request onto a bus, the access request identifying a sequence of addresses within the address range and including a control signal indicating whether the access request is a secure access request or a non-secure access request. The secure region is only accessible by a secure access request.