Abstract: A more rapid charging of an integrating capacitor of a PLL is provided when large frequency changes are desired. In one embodiment, the phase locked loop (PLL) circuit sinks or sources current to charge or discharge the integrating capacitor. A threshold voltage proportional to a current through the capacitor turns on a circuit which sinks or sources more current of the proper polarity to the integrating capacitor from an external source until a PLL lock is achieved. Once the lock is achieved, if a small correction current is required by the PLL, the small correction current is below a threshold required to actuate the augmenting circuit, and the PLL loop behaves in the usual manner as if the augmenting circuit were not present. In another embodiment, the integrating capacitor is reduced in value by switchably connecting a second capacitor in series with the integrating capacitor so that the total reduced capacitance of reduced value can be charged more quickly.

Abstract: An arrangement for selectively controlling the response time of a type II phase locked loop (PLL), especially one which includes a phase detector and an amplifier of a feedback type of integrator within an IC, comprises a controllable filter stage coupled in cascade with the amplifier. The controllable filter stage includes a filter section and a switching arrangement for selectively bypassing the filter section in response to a mode -determining control signal. In the described embodiment, the PLL controls the frequency of a local oscillator of a tuner and the second filter section has an amplitude versus frequency response for increasing the response time of the PLL during a fine tuning mode so that a demodulator can continue to operate properly during the fine tuning mode.

Abstract: An economical tuning system for a digital satellite television receiver includes a phase locked loop (PLL) tuning control IC of the which is normally used in a tuning system of a conventional terrestrial broadcast or cable television reciever to control the frequency of the local oscillator (LO). Unfortunately, the PLL IC is only capable of changing the frequency of the LO in relatively large steps. As a result, the operation of a carrier recovery loop which demodulates the digitally encoded IF signal produced by the tuner may be interrupted during a fine tuning mode because the carrier recovery loop may not be able to track frequency changes of the LO. To reduce such possibility, the integrator filter associated with the PLL IC is modified to decrease the rate of change of the LO frequency during the fine tuning mode.

Abstract: A more rapid charging of an integrating capacitor of a PLL is provided when large frequency changes are desired. In one embodiment, the phase locked loop (PLL) circuit sinks or sources current to charge or discharge the integrating capacitor. A threshold voltage proportional to a current through the capacitor turns on an augmenting circuit which sinks or sources more current of the proper polarity to the integrating capacitor from an external source until a PLL lock is achieved. Once the lock is achieved, if a small correction current is required by the PLL, the small correction current is below a threshold required to actuate the augmenting circuit, and the PLL loop behaves in the usual manner as if the augmenting circuit were not present. In another embodiment, the integrating capacitor is reduced in value by switchably connecting a second capacitor in series with the integrating capacitor so that the total reduced capacitance of reduced value can be charged more quickly.

Abstract: The invention concerns an arrangement including a microprocessor controller, PROM memory, and a digital to analog converter (DAC) arrangement for generating a plurality of control voltages for trimming respective ones of a plurality of varactor controlled tunable filters. The controller couples digital control signals to the respective DACs which generate respective analog control voltages which are applied to the respective tunable filters. A tuning voltage generated by a closed control loop, such as phased locked loop also under the control of the controller, is combined with the output control voltages generated by the respective DAC's in a resistance divider arrangement.