Abstract: A method for fabricating light emitting diode (LED) dice includes the steps of: providing a substrate, and forming a plurality of die sized semiconductor structures on the substrate. The method also includes the steps of providing a receiving plate having an elastomeric polymer layer, placing the substrate and the receiving plate in physical contact with an adhesive force applied by the elastomeric polymer layer, and performing a laser lift-off (LLO) process by directing a uniform laser beam through the substrate to the semiconductor layer at an interface with the substrate to lift off the semiconductor structures onto the elastomeric polymer layer. During the laser lift-off (LLO) process the elastomeric polymer layer functions as a shock absorber to reduce momentum transfer, and as an adhesive surface to hold the semiconductor structures in place on the receiving plate.

Abstract: A computing system identifies video data capturing an expressor depicting facial behavior. The computing system analyzes the video data to determine a type of emotion exhibited by the expressor in the video data by identifying appearance changes produced by movements of facial muscles in the video data; and determining timing characteristics of the movements of the facial muscles in the video data, the timing characteristics indicating whether the facial behavior depicted by the expressor is an authentic expression or fake expression. The computing system generates a classification of the type of emotion exhibited by the expressor based on the movements of the facial muscles and the timing characteristics of the movements. The computing system outputs the classification.

Abstract: A method for fabricating a memory device with a self-aligned trap layer and rounded active region corners is disclosed. In the present invention, an STI process is performed before any of the charge-trapping and top-level layers are formed. Immediately after the STI process, the sharp corners of the active regions are exposed. Because these sharp corners are exposed at this time, they are available to be rounded through any number of known rounding techniques. Rounding the corners improves the performance characteristics of the memory device. Subsequent to the rounding process, the charge-trapping structure and other layers can be formed by a self-aligned process.

Abstract: Semiconductor devices and methods of producing the devices are disclosed. The devices are formed by forming a gate structure on a substrate. The gate structure includes a charge trapping dielectric formed between the substrate and a first poly layer. A top dielectric is formed over the poly layer and a sidewall dielectric is formed on a side of the poly layer. A second poly layer is formed over the gate structure such that a portion of the second poly layer includes a vertical portion that is in contact with the sidewall dielectric and a top portion that is in contact with the top dielectric. The top portion of the second poly layer can then be removed through, for instance, planarization.

Abstract: Semiconductor devices and methods of producing the devices are disclosed. The devices are formed by forming a gate structure on a substrate. The gate structure includes a charge trapping dielectric formed between the substrate and a first poly layer. A top dielectric is formed over the poly layer and a sidewall dielectric is formed on a side of the poly layer. A second poly layer is formed over the gate structure such that a portion of the second poly layer includes a vertical portion that is in contact with the sidewall dielectric and a top portion that is in contact with the top dielectric. The top portion of the second poly layer can then be removed through, for instance, planarization.

Abstract: Annotation methods and systems for supporting the annotation of documents in the format of a rendering engine are provided. The annotation system allows for the adding of annotations to documents, the displaying of annotations over content of the documents, and the displaying of annotations in an annotation pane. To provide annotation support for a document, the annotation system augments the document with elements including an element with annotation engine code and elements to support the collecting and displaying of annotations. When the rendering engine renders the document, it executes the annotation engine code to effect the collecting and displaying of the annotations.

Abstract: A method for fabricating a memory device with a self-aligned trap layer and rounded active region corners is disclosed. In the present invention, an STI process is performed before any of the charge-trapping and top-level layers are formed. Immediately after the STI process, the sharp corners of the active regions are exposed. Because these sharp corners are exposed at this time, they are available to be rounded through any number of known rounding techniques. Rounding the corners improves the performance characteristics of the memory device. Subsequent to the rounding process, the charge-trapping structure and other layers can be formed by a self-aligned process.

Abstract: Semiconductor devices and methods of producing the devices are disclosed. The devices are formed by forming a gate structure on a substrate. The gate structure includes a charge trapping dielectric formed between the substrate and a first poly layer. A top dielectric is formed over the poly layer and a sidewall dielectric is formed on a side of the poly layer. A second poly layer is formed over the gate structure such that a portion of the second poly layer includes a vertical portion that is in contact with the sidewall dielectric and a top portion that is in contact with the top dielectric. The top portion of the second poly layer can then be removed through, for instance, planarization.

Abstract: A method for fabricating a memory device with a self-aligned trap layer and rounded active region corners is disclosed. In the present invention, an STI process is performed before any of the charge-trapping and top-level layers are formed. Immediately after the STI process, the sharp corners of the active regions are exposed. Because these sharp corners are exposed at this time, they are available to be rounded through any number of known rounding techniques. Rounding the corners improves the performance characteristics of the memory device. Subsequent to the rounding process, the charge-trapping structure and other layers can be formed by a self-aligned process.

Abstract: During formation of a charge trap separation in a semiconductor device, an organic material is formed over a plurality of cells. This organic material is selectively removed in order to create a flat upper surface. An etching process is performed to remove the organic material as well as a charge trap layer formed over the plurality of cells, thereby exposing underlying first oxide layers in each of the cells and forming charge trap separation. Further, because of the selective removal step, the etch results in substantially uniform wing heights among the separated cells.

Abstract: Included are embodiments for performing video analysis. Some embodiments include a system with a memory component that stores logic that, when executed by the system, causes the system to receive video content of a subject, identify a mannerism of the subject at a point in time in the video content, and determine an emotional state associated with the mannerism. In some embodiments, the logic causes the system to receive a file that correlates the mannerism with the point in time and provide a user interface that provides the video content with data from the file, such that the mannerism is provided with the data.

Abstract: A method for fabricating a memory device with a self-aligned trap layer and rounded active region corners is disclosed. In the present invention, an STI process is performed before any of the charge-trapping and top-level layers are formed. Immediately after the STI process, the sharp corners of the active regions are exposed. Because these sharp corners are exposed at this time, they are available to be rounded through any number of known rounding techniques. Rounding the corners improves the performance characteristics of the memory device. Subsequent to the rounding process, the charge-trapping structure and other layers can be formed by a self-aligned process.

Abstract: Methods of analyzing a plurality of facial expressions are disclosed that include: identifying a subject person, utilizing the subject person to create an image of a known target, removing at least one distracter expression from the target image to form a revised target image, and reviewing the revised target image with at least one third party participant to form a final target image. Additional methods of analyzing a plurality of facial expressions include: identifying a subject person, utilizing the subject person to create an image of a known target, digitizing the target image, removing at least one distracter expression from the target image to transform the target image to a revised target image, and reviewing the revised target image with at least one third party participant to transform the revised target image to a final target image.

Abstract: Methods of analyzing a plurality of facial expressions are disclosed that include: identifying a subject person, utilizing the subject person to create an image of a known target, removing at least one distracter expression from the target image to form a revised target image, and reviewing the revised target image with at least one third party participant to form a final target image. Additional methods of analyzing a plurality of facial expressions include: identifying a subject person, utilizing the subject person to create an image of a known target, digitizing the target image, removing at least one distracter expression from the target image to transform the target image to a revised target image, and reviewing the revised target image with at least one third party participant to transform the revised target image to a final target image.

Abstract: A method of planarizing a semiconductor device is provided. The semiconductor device includes a substrate, first and second components provided on the surface of the substrate, and a first material provided between and above the first and second components. The first component has a height greater than a height of the second component. The method includes performing a first polishing step on the semiconductor device to remove the first material above a top surface of the first component, to remove the first material above a top surface of the second component, and to level the top surface of the first component. The method also includes performing a second polishing step on the semiconductor device to planarize the top surfaces of the first and second components.

Abstract: A method includes forming a layer of silicon oxynitride (SiON), silicon rich nitride (SiRN) or silicon nitride (Si3N4) over a layer of semiconducting material. The method further includes forming a first layer of anti-reflective material over the layer of SiON, SiRN or Si3N4 and forming a second layer of anti-reflective material over the first layer. The method also includes using the first layer, second layer and layer of SiON, SiRN or Si3N4 as a mask when etching a pattern in the layer of semiconducting material.

Abstract: Methods of analyzing a plurality of facial expressions are disclosed that include: identifying a subject person, utilizing the subject person to create an image of a known target, removing at least one distracter expression from the target image to form a revised target image, and reviewing the revised target image with at least one third party participant to form a final target image. Additional methods of analyzing a plurality of facial expressions include: identifying a subject person, utilizing the subject person to create an image of a known target, digitizing the target image, removing at least one distracter expression from the target image to transform the target image to a revised target image, and reviewing the revised target image with at least one third party participant to transform the revised target image to a final target image.

Abstract: A method of planarizing a semiconductor device is provided. The semiconductor device includes a substrate, first and second components provided on the surface of the substrate, and a first material provided between and above the first and second components. The first component has a height greater than a height of the second component. The method includes performing a first polishing step on the semiconductor device to remove the first material above a top surface of the first component, to remove the first material above a top surface of the second component, and to level the top surface of the first component. The method also includes performing a second polishing step on the semiconductor device to planarize the top surfaces of the first and second components.

Abstract: A method of planarizing a semiconductor device is provided. The semiconductor device includes a substrate, first and second components provided on the surface of the substrate, and a first material provided between and above the first and second components. The first component has a height greater than a height of the second component. The method includes performing a first polishing step on the semiconductor device to remove the first material above a top surface of the first component, to remove the first material above a top surface of the second component, and to level the top surface of the first component. The method also includes performing a second polishing step on the semiconductor device to planarize the top surfaces of the first and second components.

Abstract: A method for forming a semiconductor device may include forming a silicon oxynitride mask layer over a first layer. The first layer may be etched using the silicon oxynitride mask layer, to form a pattern in the first layer. The pattern may be filled with a dielectric material. The dielectric material may be planarized using a ceria-based slurry and using the silicon oxynitride mask layer as a stop layer.