Abstract: The invention provides an improved architecture for credit based flow control. Briefly, the memory space within the receiving switch is separated into two parts, a statically allocated portion and a dynamically allocated portion. Packets are first placed in the dynamically allocated portion, and the credits are returned immediately. When the dynamically allocated portion has no additional space, the packets are then stored in the memory portion statically allocated to the specific virtual circuit. Credits are returned when the packets are removed from the statically allocated memory portion. This scenario allows the immediate return of credits when there is space available in the dynamically allocated memory portion. It also allows improved sharing of the overall memory since more of the overall memory can be made available to a particular virtual circuit.

Abstract: The present invention provides a system and method for utilizing the Advanced Switching network protocol to communicate over long distances, such as multiple kilometers. The present invention utilizes an existing status bit, referred to as the Perishable Bit, within the AS packet header, to reduce the number of packets which must be stored in the retry buffer. This reduces the required size of the retry buffer and simultaneously reduces the latency associated with retransmitting time critical packets after NAKs are received. The receiving device also utilizes the Perishable Bit in determining which packets to accept and which to discard.

Abstract: The present invention relates generally to a generic fabric interconnect system and method for providing a data path between and among nodes and processing elements within an interconnection fabric.

Abstract: The invention provides an improved architecture for credit based flow control. Briefly, the memory space within the receiving switch is separated into two parts, a statically allocated portion and a dynamically allocated portion. Packets are first placed in the dynamically allocated portion, and the credits are returned immediately. When the dynamically allocated portion has no additional space, the packets are then stored in the memory portion statically allocated to the specific virtual circuit. Credits are returned when the packets are removed from the statically allocated memory portion. This scenario allows the immediate return of credits when there is space available in the dynamically allocated memory portion. It also allows improved sharing of the overall memory since more of the overall memory can be made available to a particular virtual circuit.

Abstract: The invention provides a system and method for identifying and communicating congested paths throughout a network fabric. Briefly, the present invention augments the congestion management mechanism defined in ASI to allow for the communication of congested paths through the fabric, rather than the simple congested output port notification supported today through the use of DLLPs. Further, it also uses the communication mechanisms already defined in the ASI specification to implement this additional capability. Specifically, the present invention uses Transaction Layer Packets (TLPs) to communicate the information concerning congested flows throughout the network. This packet type allows the inclusion of much more information than DLLPs, allowing a more comprehensive and elegant solution to the issue of congestion management in an Advanced Switching network fabric.

Abstract: The present invention minimizes the amount of traffic that traverses the fabric in support of the cache coherency protocol. It also allows rapid transmission of all traffic associated with the cache coherency protocol, so as to minimize latency and maximize performance. A fabric is used to interconnect a number of processing units together. The switches are able to recognize incoming traffic related to the cache coherency protocol and then move these messages to the head of that switch's output queue to insure fast transmission. Also, the traffic related to the cache coherency protocol can interrupt an outgoing message, further reducing latency. The switch incorporates a memory element, dedicated to the cache coherency protocol, which tracks the contents of all of the caches of all of the processors connected to the fabric. In this way, the fabric can selectively transmit traffic only to the processors where it is relevant.

Abstract: The invention utilizes a separate queue per output port as implemented in the traditional simple queuing schemes of the prior art. Further, it also uses the information found in the packet header to determine the output port and the next output port. Based on this information, it utilizes queues dedicated to congested flows, or “Congested Flow” queues. When the switch determines that, based on the first output port and the second subsequent output port, a packet in the output queue is destined for a congested path, it sets the offending packet aside in a Congested Flow queue, thereby allowing other packets destined for the first output port to continue to be transmitted. In this way, the HOL blocking issue is addressed, without the need for a significantly increased number of output queues.

Abstract: The present invention relates generally to a generic fabric interconnect system and method for providing a data path between and among nodes and processing elements within an interconnection fabric.

Abstract: The present invention relates generally to a generic fabric interconnect system and method for providing a data path between and among nodes and processing elements within an interconnection fabric.

Abstract: A method for accessing a configuration space of a device is described. The method includes setting a first field of a packet to a value to specify a destination device, and setting a second field of the packet to a defined value to indicate that the packet is a configuration access packet. The method further includes setting a third field of the configuration access packet to a value to select one of a plurality of configuration apertures of a configuration space of the destination device, and setting a fourth field of the configuration access packet to a value to address a specific memory location within the selected aperture.

Abstract: A queuing mechanism is described for managing packets between agents of a computer system. The queuing mechanism includes an ordered queue including a plurality of queue registers to store a plurality of packets. The queuing mechanism also includes a bypass queue coupled to the ordered queue, wherein, if a packet at head of the ordered queue is a delayed request and is stalled for lack of flow control credit, then the stalled packet is moved into the bypass queue.

Abstract: A system and method for transferring data between two relatively autonomous processors using a sockets interface. In particular, a source SDT (“socket data transfer”) engine tells a destination SDT engine that data is available. Next the destination SDT engine then sends a data request to the source SDT engine. The source SDT engine then sends data to the destination SDT engine.

Abstract: A structural panel for use in building construction and other applications has an internal rib structure with the ribs interlocked to form a two dimensional matrix. The ribs have tabs that are fitted into openings of facing sheets of the panels. This structure results in a strong prefabricated building panel.