Abstract: Systems and methods for priority encoded domains in an SoC have been described. In an illustrative, non-limiting embodiment, a processing system in an SoC, may include: a core, and a domain access controller coupled to the core. The domain access controller may be configured to: receive a resource transaction request from a master device associated with a software-defined processing domain, and process the resource transaction request based upon a priority level of the software-defined processing domain. The domain access controller may also order a plurality of resource transaction requests based upon the associated respective priority levels, and provide the resource transaction requests to resources based on the order. A hypervisor can also use the priority levels of the software-defined processing domains to allocate a plurality of virtual machines to a plurality of processing cores according to the priority levels.

Abstract: A direct memory access (DMA) router including interrupt inputs, action groups and a DMA router engine. Each interrupt input is configured to receive a corresponding interrupt signal. Each action group is associated with a corresponding interrupt input and is configured with at least one DMA action, in which each DMA action is configured to select a DMA controller and a corresponding channel. The DMA router is configured to initiate a transfer using a selected channel of a selected DMA controller for at least one DMA action listed in an action group associated with a corresponding interrupt input triggered by assertion of a corresponding interrupt signal. The DMA actions may indicate dependencies, such that the DMA router may initiate a second DMA action only after completion of a first DMA action within the same action group based upon the indicated dependency.

Abstract: A communication interface includes a first and second interface module to provide for point-to-point transmission of signalling to a second or third node respectively and receipt of signalling from the second node or third node respectively via one or more first terminals. The first and second interface modules include one or more second terminals to communicatively couple a first processor and the first or second interface module. At least one interface-to-interface connection couples the first interface module and the second interface module. A routing module reads a data frame and, based on whether or not an identifier present in a routing field of the data frame matches one or more predetermined identifiers, provides for forwarding of the data frame to the first processor or to the interface-to-interface connection for retransmission by the other of the first interface module and the second interface module.

Abstract: Systems and methods for priority encoded domains in an SoC have been described. In an illustrative, non-limiting embodiment, a processing system in an SoC, may include: a core, and a domain access controller coupled to the core. The domain access controller may be configured to: receive a resource transaction request from a master device associated with a software-defined processing domain, and process the resource transaction request based upon a priority level of the software-defined processing domain. The domain access controller may also order a plurality of resource transaction requests based upon the associated respective priority levels, and provide the resource transaction requests to resources based on the order. A hypervisor can also use the priority levels of the software-defined processing domains to allocate a plurality of virtual machines to a plurality of processing cores according to the priority levels.

Abstract: A processing system includes an interconnect, a master processing device including processing cores coupled to the interconnect, a hypervisor coupled to the interconnect and configured to allocate the processing cores to one or more virtual machines, domain configuration information including a domain identifier for each of the one or more virtual machines, remote peripheral devices coupled to the interconnect, and a domain access controller coupled to the interconnect and configured to receive the domain identifiers for the remote peripherals directly from the hypervisor through the interconnect.

Abstract: This invention generally provides blocked isocyanate compositions and more specially blocked isocyanate compositions useful in aminoplastic resins, phenoplastic resins or latex resins for composite wood products, wherein the blocked isocyanate composition is obtained by adding alkylene carbonate to a blocked isocyanate (A), wherein the blocked isocyanate (A) is obtained by reacting a secondary amine (a1) with a reaction product (a2) of a polyfunctional isocyanate and a monofunctional hydroxyl containing compound, wherein the monofunctional hydroxyl containing compound is a polyethylene oxide polymer with terminal hydroxyl group, polyoxyethylene-polyoxypropylene monols or a mixture thereof, wherein the portion of blocked isocyanate (A) by weight percentage of the blocked isocyanate composition is between 50 and 90, preferably between 60 and 80. The compositions are stable at room temperature when mixed with active hydrogen containing compounds.

Abstract: A processing system includes an interconnect, a master processing device including processing cores coupled to the interconnect, a hypervisor coupled to the interconnect and configured to allocate the processing cores to one or more virtual machines, domain configuration information including a domain identifier for each of the one or more virtual machines, remote peripheral devices coupled to the interconnect, and a domain access controller coupled to the interconnect and configured to receive the domain identifiers for the remote peripherals directly from the hypervisor through the interconnect.

Abstract: An error recovery system, method, and apparatus are provided for a microcontroller unit (100) having a plurality of components (101-109) by assigning error recovery actions to at least a first MCU component to specify a component-specific operation for returning the first MCU component to a known state to restart operation of the first MCU component from the known state, and then storing the assigned error recovery actions in a recovery lookup table (122) so that a fault collection and control unit can use a hardware state machine (121) to evaluate an error signal received from an MCU component for determining an error type and location for the MCU component which are applied to the recovery lookup table to retrieve and apply the error recovery actions to return the first MCU component to the known state without restarting all other components on the MCU.

Abstract: This invention generally provides blocked isocyanate compositions and more specially blocked isocyanate compositions useful in aminoplastic resins, phenoplastic resins or latex resins for composite wood products, wherein the blocked isocyanate composition is obtained by adding alkylene carbonate to a blocked isocyanate (A), wherein the blocked isocyanate (A) is obtained by reacting a secondary amine (a1) with a reaction product (a2) of a polyfunctional isocyanate and a monofunctional hydroxyl containing compound, wherein the monofunctional hydroxyl containing compound is a polyethylene oxide polymer with terminal hydroxyl group, polyoxyethylene-polyoxypropylene monols or a mixture thereof, wherein the portion of blocked isocyanate (A) by weight percentage of the blocked isocyanate composition is between 50 and 90, preferably between 60 and 80. The compositions are stable at room temperature when mixed with active hydrogen containing compounds.