Abstract: An integrated circuit includes a multiplexer circuit coupled to receive a first clock signal and a second clock signal and coupled to provide an output clock signal to a channel. A protection circuit is coupled to receive a feedback signal from the channel. The protection circuit causes the multiplexer circuit to provide oscillations in the second clock signal to the output clock signal in response to the feedback signal indicating that the channel is idle to cause the channel to be in a protection mode that reduces degradation from bias temperature instability. The protection circuit causes the multiplexer circuit to provide oscillations in the first clock signal to the output clock signal in response to the feedback signal indicating that the channel is active.

Abstract: A data transmission system includes a transmitter circuit. The transmitter circuit receives regular data bits and auxiliary data bits. The transmitter circuit encodes a first subset of the regular data bits to generate a first subset of encoded data comprising pairs of symbols that are used in quadrature amplitude modulation. The transmitter circuit encodes the auxiliary data bits and a second subset of the regular data bits to generate a second subset of the encoded data comprising at least one pair of symbols that are unused for encoding by the quadrature amplitude modulation. The transmitter circuit generates a modulated output signal that indicates the first and second subsets of the encoded data using pulse amplitude modulation.

Abstract: An integrated circuit includes a multiplexer circuit coupled to receive a first clock signal and a second clock signal and coupled to provide an output clock signal to a channel. A protection circuit is coupled to receive a feedback signal from the channel. The protection circuit causes the multiplexer circuit to provide oscillations in the second clock signal to the output clock signal in response to the feedback signal indicating that the channel is idle to cause the channel to be in a protection mode that reduces degradation from bias temperature instability. The protection circuit causes the multiplexer circuit to provide oscillations in the first clock signal to the output clock signal in response to the feedback signal indicating that the channel is active.

Abstract: A data transmission system includes a transmitter circuit. The transmitter circuit receives regular data bits and auxiliary data bits. The transmitter circuit encodes a first subset of the regular data bits to generate a first subset of encoded data comprising pairs of symbols that are used in quadrature amplitude modulation. The transmitter circuit encodes the auxiliary data bits and a second subset of the regular data bits to generate a second subset of the encoded data comprising at least one pair of symbols that are unused for encoding by the quadrature amplitude modulation. The transmitter circuit generates a modulated output signal that indicates the first and second subsets of the encoded data using pulse amplitude modulation.

Abstract: An integrated circuit includes a signal network and a phase detector circuit. The signal network includes an adjustable delay circuit. The adjustable delay circuit is coupled at an intersection in the signal network between branches of the signal network. The signal network generates a first signal at a first leaf node of the signal network in response to a second signal. The signal network generates a third signal at a second leaf node of the signal network in response to the second signal. The phase detector circuit compares phases of the first and third signals to generate a phase detection signal. The adjustable delay circuit adjusts a delay provided to the first signal relative to the second signal to reduce a skew between the first and third signals based on the phase detection signal indicating that the first and third signals have the skew.

Abstract: An integrated circuit includes a signal network and a phase detector circuit. The signal network includes an adjustable delay circuit. The adjustable delay circuit is coupled at an intersection in the signal network between branches of the signal network. The signal network generates a first signal at a first leaf node of the signal network in response to a second signal. The signal network generates a third signal at a second leaf node of the signal network in response to the second signal. The phase detector circuit compares phases of the first and third signals to generate a phase detection signal. The adjustable delay circuit adjusts a delay provided to the first signal relative to the second signal to reduce a skew between the first and third signals based on the phase detection signal indicating that the first and third signals have the skew.

Abstract: An integrated circuit includes a signal network and a phase detector circuit. The signal network includes an adjustable delay circuit. The adjustable delay circuit is coupled at an intersection in the signal network between branches of the signal network. The signal network generates a first signal at a first leaf node of the signal network in response to a second signal. The signal network generates a third signal at a second leaf node of the signal network in response to the second signal. The phase detector circuit compares phases of the first and third signals to generate a phase detection signal. The adjustable delay circuit adjusts a delay provided to the first signal relative to the second signal to reduce a skew between the first and third signals based on the phase detection signal indicating that the first and third signals have the skew.

Abstract: First and second circuits in an integrated circuit that generate local hot spots are activated at different times in order to reduce heat generation within each of the first and second circuits. The first and second circuits in the integrated circuit have the same circuit architecture. The first circuit processes data during a first time period, and heat generation is reduced in the second circuit during the first time period. A data path of the data is then switched from the first circuit to the second circuit. The second circuit then processes the data during a second time period after the first time period, and heat generation is reduced in the first circuit during the second time period. The data path of the data is then switched from the second circuit back to the first circuit. The first circuit then processes the data again.

Abstract: First and second circuits in an integrated circuit that generate local hot spots are activated at different times in order to reduce heat generation within each of the first and second circuits. The first and second circuits in the integrated circuit have the same circuit architecture. The first circuit processes data during a first time period, and heat generation is reduced in the second circuit during the first time period. A data path of the data is then switched from the first circuit to the second circuit. The second circuit then processes the data during a second time period after the first time period, and heat generation is reduced in the first circuit during the second time period. The data path of the data is then switched from the second circuit back to the first circuit. The first circuit then processes the data again.

Abstract: An integrated circuit includes first and second data channel circuits and first and second inductor-capacitor (LC) tank oscillator circuits. The first data channel circuit generates a first data signal in response to a first clock signal. The second data channel circuit generates a second data signal in response to a second clock signal. The frequencies of the first and second clock signals are substantially the same. The first LC tank oscillator circuit generates a first periodic signal. The first clock signal is generated in response to the first periodic signal. The second LC tank oscillator circuit generates a second periodic signal. The second clock signal is generated in response to the second periodic signal. The first and second LC tank oscillator circuits generate non-overlapping frequency ranges for the first and second periodic signals.

Abstract: An apparatus includes an encoder adapted to encode data bits for transmission via a communication link. The encoder includes a logic circuit. The logic circuit is adapted to perform a logic operation on a pattern of bits and the data bits in order to reduce a run-length of the data bits.

Abstract: Receiver circuits in serial lanes each generate a synchronous clock signal that is aligned with a master clock signal to allow synchronous transfer of data onto the master clock domain without corruption. A serial-to-parallel converter circuit in each receiver circuit converts a serial data signal into parallel data signals in response to one of the synchronous clock signals. Phase detection circuitry generates an indication of a phase shift based on a phase offset between the synchronous and master clock signals. A clock signal generation circuit provides an adjustment to a phase of the synchronous clock signal based on the indication of the phase shift. The serial-to-parallel converter circuit adjusts positions of bits indicated by the parallel data signals based on the adjustment to the phase of the synchronous clock signal.

Abstract: A method and system for reducing power consumption in a programmable logic device (PLD) is provided. The power consumption may be reduced by preferably continually considering power consumption as a factor in circuit design during the synthesis, placement, routing, and period following routing of the programmable logic device.

Abstract: A method and system for reducing power consumption in a programmable logic device (PLD) is provided. The power consumption may be reduced by preferably continually considering power consumption as a factor in circuit design during the technology mapping, routing, and period following routing of the programmable logic device.

Abstract: The present invention provides kinase inhibitors of Formula I.

Abstract: The present invention provides kinase inhibitors of Formula I.

Abstract: The present invention provides kinase inhibitors of Formula I.

Abstract: This application relates to a compound of formula (I) (or a pharmaceutically acceptable salt of the compound or prodrug thereof) as defined herein, pharmaceutical compositions thereof, and its use as an inhibitor of factor Xa and/or thrombin, as well as a process for its preparation and intermediates therefor. An example of a compound of formula (I) is (a).

Abstract: The present invention provides compounds that are inhibitors of VEGF-R2 of the formula: (I) and methods of using these compounds.

Abstract: This application relates to a compound of formula (I) (or a pharmaceutically acceptable salt of the compound) as defined herein, pharmaceutical compositions thereof, and its use as an inhibitor of factor Xa and/or thrombin, as well as a process for its preparation and intermediates therefor.