Abstract: An apparatus includes a first phase on-timer configured to produce a first reset signal for determining a turn-off time instant of a high-side switch of a first phase of a power converter, a feedback control circuit configured to produce a first set signal for determining a turn-on time instant of the high-side switch of the first phase of the power converter, a second phase on-timer configured to produce a second reset signal for determining a turn-off time instant of a high-side switch of a second phase of the power converter, and a delay generator configured to produce a delay signal for determining a phase shift between the first phase and the second phase of the power converter.

Abstract: A controller includes a current-mode control device configured to determine a turn-on edge of a first gate-drive signal, an on-time timer that includes a first ramp generator having a first current source, a first capacitor, and a first ramp-generation switch, the first ramp generator configured to generate a first ramp signal, and a first logic circuit having an output coupled to a control terminal of the first ramp-generation switch, the first logic circuit configured to control the first ramp-generation switch based at least in part on the first gate-drive signal and on a feedback signal received from the current-mode control device, thereby resetting the first ramp signal, wherein the on-time timer is further configured to determine a turn-off edge of the first gate-drive signal by comparing the first ramp signal with a first threshold voltage that is proportional to an output voltage of the power converter.

Abstract: An apparatus includes a buck converter portion of a buck-boost converter configured to operate under a constant on-time control scheme, wherein an on-time of a high-side switch of the buck converter portion is determined by a buck on-time timer, and a boost converter portion of the buck-boost converter configured to operate under a constant off-time control scheme, wherein an off-time of a low-side switch of the boost converter portion is determined by a boost off-time timer.

Abstract: An apparatus includes a ramp generator configured to produce a set signal for determining a phase shift between a first phase and a second phase of a power converter, a first phase on-timer configured to produce a first reset signal for determining a turn-on time of a high-side switch of the first phase of the power converter, a second phase on-timer configured to produce a second reset signal for determining a turn-on time of a high-side switch of the second phase of the power converter, and a control logic block configured to generate gate drive signals for the first phase and the second phase of the power converter based on the set signal, the first reset signal and the second reset signal.

Abstract: An apparatus includes a transistor coupled to a load through an output terminal of a load switch IC, a gate drive circuit connected to a gate of the transistor, wherein the gate drive circuit is configured such that in a short circuit event, a voltage on the gate of the transistor is gradually reduced, and wherein as a result of reducing the voltage on the gate of the transistor gradually, a negative voltage occurring at the output terminal of the load switch IC is minimized.

Abstract: An apparatus includes a ramp generator configured to produce a set signal for determining a phase shift between a first phase and a second phase of a power converter, a first phase on-timer configured to produce a first reset signal for determining a turn-on time of a high-side switch of the first phase of the power converter, a second phase on-timer configured to produce a second reset signal for determining a turn-on time of a high-side switch of the second phase of the power converter, and a control logic block configured to generate gate drive signals for the first phase and the second phase of the power converter based on the set signal, the first reset signal and the second reset signal.

Abstract: An apparatus includes a ramp generator configured to produce a set signal for determining a phase shift between a first phase and a second phase of a power converter, a first phase on-timer configured to produce a first reset signal for determining a turn-on time of a high-side switch of the first phase of the power converter, a second phase on-timer configured to produce a second reset signal for determining a turn-on time of a high-side switch of the second phase of the power converter, and a control logic block configured to generate gate drive signals for the first phase and the second phase of the power converter based on the set signal, the first reset signal and the second reset signal.

Abstract: An apparatus includes a buck converter portion of a buck-boost converter configured to operate under a constant on-time control scheme, wherein an on-time of a high-side switch of the buck converter portion is determined by a buck on-time timer, and a boost converter portion of the buck-boost converter configured to operate under a constant off-time control scheme, wherein an off-time of a low-side switch of the boost converter portion is determined by a boost off-time timer.

Abstract: An apparatus includes a buck converter portion of a buck-boost converter configured to operate under a constant on-time control scheme, wherein an on-time of a high-side switch of the buck converter portion is determined by a buck on-time timer, and a boost converter portion of the buck-boost converter configured to operate under a constant off-time control scheme, wherein an off-time of a low-side switch of the boost converter portion is determined by a boost off-time timer.

Abstract: An apparatus includes a first timer configured to determine a turn-off time of a first high-side switch of a buck-boost converter, and a second timer configured to determine a turn-off time of a second low-side switch of the buck-boost converter based on a comparison between a first signal and a second signal, the first signal being proportional to an input voltage of the buck-boost converter, and the second signal being generated based on a signal proportional to an output voltage of the buck-boost converter.

Abstract: An apparatus includes a ramp generator configured to produce a set signal for determining a phase shift between a first phase and a second phase of a power converter, a first phase on-timer configured to produce a first reset signal for determining a turn-on time of a high-side switch of the first phase of the power converter, a second phase on-timer configured to produce a second reset signal for determining a turn-on time of a high-side switch of the second phase of the power converter, and a control logic block configured to generate gate drive signals for the first phase and the second phase of the power converter based on the set signal, the first reset signal and the second reset signal.

Abstract: An apparatus includes a transistor coupled to a load through an output terminal of a load switch IC, a gate drive circuit connected to a gate of the transistor, wherein the gate drive circuit is configured such that in a short circuit event, a voltage on the gate of the transistor is gradually reduced, and wherein as a result of reducing the voltage on the gate of the transistor gradually, a negative voltage occurring at the output terminal of the load switch IC is minimized.

Abstract: An apparatus includes a buck-boost converter comprising a buck portion and a boost portion connected in cascade, and a controller comprising a first timer and a second timer, wherein the first timer is configured to determine a turn-on time of a high-side switch of the buck portion, and wherein the first timer determines the turn-on time of the high-side switch of the buck portion based on a comparison between a first signal and a second signal, and wherein the first signal is proportional to an output voltage of the buck-boost converter and the second signal is generated based on a signal proportional to an input voltage of the buck-boost converter, and the second timer is configured to determine a turn-on time of a low-side switch of the boost portion.

Abstract: An apparatus includes a buck converter portion of a buck-boost converter configured to operate under a constant on-time control scheme, wherein an on-time of a high-side switch of the buck converter portion is determined by a buck on-time timer, and a boost converter portion of the buck-boost converter configured to operate under a constant off-time control scheme, wherein an off-time of a low-side switch of the boost converter portion is determined by a boost off-time timer.

Abstract: An apparatus includes a first timer configured to determine a turn-off time of a first high-side switch of a buck-boost converter, and a second timer configured to determine a turn-off time of a second low-side switch of the buck-boost converter based on a comparison between a first signal and a second signal, the first signal being proportional to an input voltage of the buck-boost converter, and the second signal being generated based on a signal proportional to an output voltage of the buck-boost converter.

Abstract: A buck-boost converter comprises generating a first ramp using a first current source having a current level proportional to an input voltage of a buck-boost converter, and a second ramp using a second current source having a current level proportional to an output voltage of the buck-boost converter, generating a first threshold voltage proportional to a difference between the input voltage and the output voltage of the buck-boost converter, and a second threshold voltage proportional to the input voltage of the buck-boost converter, terminating a gate drive signal of a first low-side switch of the buck-boost converter based upon comparing the first threshold voltage and the first ramp, and terminating a gate drive signal of a second high-side switch of the buck-boost converter based upon comparing the second threshold voltage and the second ramp.

Abstract: An apparatus includes a buck-boost converter comprising a buck portion and a boost portion connected in cascade, and a controller comprising a first timer and a second timer, wherein the first timer is configured to determine a turn-on time of a high-side switch of the buck portion, and wherein the first timer determines the turn-on time of the high-side switch of the buck portion based on a comparison between a first signal and a second signal, and wherein the first signal is proportional to an output voltage of the buck-boost converter and the second signal is generated based on a signal proportional to an input voltage of the buck-boost converter, and the second timer is configured to determine a turn-on time of a low-side switch of the boost portion.

Abstract: A controller includes a first timer for setting a turn-on time of a first high-side switch of a buck-boost converter, wherein the turn-on time of the first high-side switch is determined by an input voltage of the buck-boost converter, an output voltage of the buck-boost converter and a first predetermined bias voltage, a second timer for setting a turn-on time of a second low-side switch of the buck-boost converter, wherein the turn-on time of the second low-side switch is determined by the input voltage of the buck-boost converter, the output voltage of the buck-boost converter and a second predetermined bias voltage, and a valley current mode control device for setting a turn-on time of a first low-side switch and a turn-on time of a second high-side switch of the buck-boost converter.

Abstract: A power converter comprises a first switch and a second switch connected in series between an input power source and ground, an inductor connected between a common node of the first switch and the second switch, and an output capacitor, a control apparatus comprising a feedback control apparatus and an ramp generator, wherein the ramp generator is configured to dynamically adjust an amplitude of a ramp based upon different operating conditions, an on-time control generator and a latch having a set input configured to receive an output signal of the control apparatus and a reset input configured to receive an output signal of the on-time control generator.

Abstract: A buck-boost converter comprises generating a first ramp using a first current source having a current level proportional to an input voltage of a buck-boost converter, and a second ramp using a second current source having a current level proportional to an output voltage of the buck-boost converter, generating a first threshold voltage proportional to a difference between the input voltage and the output voltage of the buck-boost converter, and a second threshold voltage proportional to the input voltage of the buck-boost converter, terminating a gate drive signal of a first low-side switch of the buck-boost converter based upon comparing the first threshold voltage and the first ramp, and terminating a gate drive signal of a second high-side switch of the buck-boost converter based upon comparing the second threshold voltage and the second ramp.