Patents by Inventor David Michael Friend
David Michael Friend has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8686782Abstract: The present invention provides an apparatus and method for a frequency adaptive level shifter circuit. The frequency adaptive level shifter circuit includes a first inverter, a second inverter coupled to the output of the first inverter, a capacitor coupled to the output of the second inverter, and a resistor coupled to the output of the capacitor. The frequency adaptive level shifter circuit further includes a transistor coupled to the output of the resistor, wherein the transistor has a gate connected to a reference voltage, a third inverter coupled to the output of the capacitor, and a fourth inverter coupled to the output of the third inverter and the transistor and outputting the signal.Type: GrantFiled: November 30, 2010Date of Patent: April 1, 2014Assignee: International Business Machines CorporationInventors: Joel Thomas Ficke, David Michael Friend, Grant Paul Kesselring, James David Strom, Jianguo Yao
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Patent number: 8373486Abstract: The present invention provides an apparatus and method for a frequency adaptive level shifter circuit. The frequency adaptive level shifter circuit includes a first inverter, a second inverter coupled to the output of the first inverter, a capacitor coupled to the output of the second inverter, and a resistor coupled to the output of the capacitor. The frequency adaptive level shifter circuit further includes a transistor coupled to the output of the resistor, wherein the transistor has a gate connected to a reference voltage, a third inverter coupled to the output of the capacitor, and a fourth inverter coupled to the output of the third inverter and the transistor and outputting the signal.Type: GrantFiled: March 27, 2012Date of Patent: February 12, 2013Assignee: International Business Machines CorporationInventors: Joel Thomas Ficke, David Michael Friend, Grant Paul Kesselring, James David Strom, Jianguo Yao
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Publication number: 20120187987Abstract: The present invention provides an apparatus and method for a frequency adaptive level shifter circuit. The frequency adaptive level shifter circuit includes a first inverter, a second inverter coupled to the output of the first inverter, a capacitor coupled to the output of the second inverter, and a resistor coupled to the output of the capacitor. The frequency adaptive level shifter circuit further includes a transistor coupled to the output of the resistor, wherein the transistor has a gate connected to a reference voltage, a third inverter coupled to the output of the capacitor, and a fourth inverter coupled to the output of the third inverter and the transistor and outputting the signal.Type: ApplicationFiled: March 27, 2012Publication date: July 26, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Joel Thomas Ficke, David Michael Friend, Grant Paul Kesselring, James David Strom, Jianguo Yao
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Publication number: 20120133413Abstract: The present invention provides an apparatus and method for a frequency adaptive level shifter circuit. The frequency adaptive level shifter circuit includes a first inverter, a second inverter coupled to the output of the first inverter, a capacitor coupled to the output of the second inverter, and a resistor coupled to the output of the capacitor. The frequency adaptive level shifter circuit further includes a transistor coupled to the output of the resistor, wherein the transistor has a gate connected to a reference voltage, a third inverter coupled to the output of the capacitor, and a fourth inverter coupled to the output of the third inverter and the transistor and outputting the signal.Type: ApplicationFiled: November 30, 2010Publication date: May 31, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Joel Thomas Ficke, David Michael Friend, Grant Paul Kesselring, James David Strom, Jianguo Yao
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Patent number: 6990510Abstract: Apparatus and method for performing fast arithmetic operations, including addition, in a pipelined circuit. In one embodiment, the apparatus comprises a plurality of gates, the critical path through the plurality of gates being three gates delays for some embodiments. The apparatus may comprise: a first level of logic for receiving at least two binary numbers and generating multi-bit P, G, Z, and K carry signals; a second level of logic receiving the multi-bit P, G, Z, and K carry signals and generating multi-bit section-based carry signals; and a third level of logic receiving the multi-bit section-based carry signals and generating a sum of the received binary numbers, the third level of logic comprising: a plurality of domino logic gates forming sum bits using the multi-bit section-based P, G, Z, and K carry signals.Type: GrantFiled: January 22, 2002Date of Patent: January 24, 2006Assignee: International Business Machines CorporationInventors: David Michael Friend, David Arnold Luick, Nghia Van Phan
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Patent number: 6909159Abstract: Methods and apparatus are provided for reducing the overall radiation hardness of a semiconductor chip. A radiation detector and a failure memory are provided. A disable signal or signals is produced by the failure memory. The disable signal is a required input to a user logic function, such as an off chip driver, an off chip receiver, a clock, or a static random access memory. When the radiation detector detects radiation, that detection is stored in the failure memory. The disable signal, when active, causes some or all of the user function to be inoperative. This invention is particularly important when the semiconductor chip is produced in a silicon on insulator (SOI) Complementary Metal Oxide Semiconductor (CMOS) process, which is naturally radiation resistant.Type: GrantFiled: June 20, 2002Date of Patent: June 21, 2005Assignee: International Business Machines CorporationInventors: David Michael Friend, Nghia Van Phan, Michael James Rohn
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Publication number: 20030234430Abstract: Methods and apparatus are provided for reducing the overall radiation hardness of a semiconductor chip. A radiation detector and a failure memory are provided. A disable signal or signals is produced by the failure memory. The disable signal is a required input to a user logic function, such as an off chip driver, an off chip receiver, a clock, or a static random access memory. When the radiation detector detects radiation, that detection is stored in the failure memory. The disable signal, when active, causes some or all of the user function to be inoperative. This invention is particularly important when the semiconductor chip is produced in a silicon on insulator (SOI) Complementary Metal Oxide Semiconductor (CMOS) process, which is naturally radiation resistant.Type: ApplicationFiled: June 20, 2002Publication date: December 25, 2003Applicant: International Business Machines CorporationInventors: David Michael Friend, Nghia Van Phan, Michael James Rohn
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Patent number: 6668358Abstract: A method is disclosed wherein a subset of logic blocks on an ASIC simiconductor logic chip is examined for replacement by functionally equivalent logic blocks in the ASIC library. The functionally equivalent logic block replacements are designed to exhibit, on average, significantly less subthreshold leakage currents. The replacement blocks are slower performing blocks, and therefore, checks are made to ensure that timing requirements are not violated.Type: GrantFiled: October 1, 2001Date of Patent: December 23, 2003Assignee: International Business Machines CorporationInventors: David Michael Friend, Nghia Van Phan, Byron D. Scott, Daniel Lawrence Stasiak, Bradley Craig White
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Publication number: 20030205759Abstract: A method and apparatus for reducing parasitic bipolar transistor leakage current in a Silicon on Insulator (SOI) Metal Oxide Semiconductor (MOS). A capacitor is operatively coupled between the base and emitter terminals of the parasitic bipolar transistor. The capacitor effectively reduces the base to emitter voltage of the parasitic transistor thereby reducing leakage current generated at the collector terminal.Type: ApplicationFiled: October 23, 2001Publication date: November 6, 2003Applicant: International Business Machines CorporationInventors: Todd Alan Christensen, David Michael Friend, Nghia Van Phan, John Edward Sheets
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Publication number: 20030140080Abstract: Apparatus and method for performing fast arithmetic operations, including addition, in a pipelined circuit. In one embodiment, the apparatus comprises a plurality of gates, the critical path through the plurality of gates being three gates delays for some embodiments. The apparatus may comprise: a first level of logic for receiving at least two binary numbers and generating multi-bit P, G, Z, and K carry signals; a second level of logic receiving the multi-bit P, G, Z, and K carry signals and generating multi-bit section-based carry signals; and a third level of logic receiving the multi-bit section-based carry signals and generating a sum of the received binary numbers, the third level of logic comprising: a plurality of domino logic gates forming sum bits using the multi-bit section-based P, G, Z, and K carry signals.Type: ApplicationFiled: January 22, 2002Publication date: July 24, 2003Applicant: International Business Machines CorporationInventors: David Michael Friend, David Arnold Luick, Nghia Van Phan
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Publication number: 20030071692Abstract: Measurement methods and a ring oscillator circuit are provided for evaluating dynamic circuits. The ring oscillator circuit includes a one-shot pulse generator receiving a single transition input signal and producing a pulse output signal having a rising transition and falling transition. The dynamic circuit to be evaluated is coupled to an output of the one-shot pulse generator receiving the pulse output signal of the one-shot pulse generator and producing a delayed output pulse at an output. A divide-by-two circuit is coupled to the output of the dynamic circuit to be evaluated. An output signal of the divide-by-two circuit is fed back to the one-shot pulse generator, and the cycle is repeated, thus oscillating. A multiplexer is connected between output of the dynamic circuit to be evaluated and the divide-by-two circuit.Type: ApplicationFiled: October 15, 2001Publication date: April 17, 2003Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Anthony Gus Aipperspach, Todd Alan Christensen, Peter Thomas Freiburger, David Michael Friend, Nghia Van Phan
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Publication number: 20030070147Abstract: A method is disclosed wherein a subset of logic blocks on an ASIC simiconductor logic chip is examined for replacement by functionally equivalent logic blocks in the ASIC library. The functionally equivalent logic block replacements are designed to exhibit, on average, significantly less subthreshold leakage currents. The replacement blocks are slower performing blocks, and therefore, checks are made to ensure that timing requirements are not violated.Type: ApplicationFiled: October 1, 2001Publication date: April 10, 2003Applicant: International Business Machines CorporationInventors: David Michael Friend, Nghia Van Phan, Byron D. Scott, Daniel Lawrence Stasiak, Bradley Craig White
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Patent number: 6538522Abstract: Measurement methods and a ring oscillator circuit are provided for evaluating dynamic circuits. The ring oscillator circuit includes a one-shot pulse generator receiving a single transition input signal and producing a pulse output signal having a rising transition and falling transition. The dynamic circuit to be evaluated is coupled to an output of the one-shot pulse generator receiving the pulse output signal of the one-shot pulse generator and producing a delayed output pulse at an output. A divide-by-two circuit is coupled to the output of the dynamic circuit to be evaluated. An output signal of the divide-by-two circuit is fed back to the one-shot pulse generator, and the cycle is repeated, thus oscillating. A multiplexer is connected between output of the dynamic circuit to be evaluated and the divide-by-two circuit.Type: GrantFiled: October 15, 2001Date of Patent: March 25, 2003Assignee: International Business Machines CorporationInventors: Anthony Gus Aipperspach, Todd Alan Christensen, Peter Thomas Freiburger, David Michael Friend, Nghia Van Phan