Abstract: Aspects of the present disclosure relate to an apparatus comprising processing circuitry to process inputs, the processing circuitry comprising a plurality of sequential stages; clocked input circuitry to receive a flow of clocked inputs and provide said clocked inputs to the processing circuitry, said clocked inputs being synchronised with one or more clock signal of the processing circuitry; and asynchronous input circuitry to receive an asynchronous input and provide said asynchronous input to the processing circuitry. The asynchronous input is a deactivation signal to direct the processing circuitry to cease processing clocked inputs. Clock circuitry provides said one or more clock signals, said clock circuitry being responsive to said deactivation signal to control a deactivation of the one or more clock signals such that each of said plurality of sequential stages undergoes a respective corresponding number of clock cycles.

Abstract: An apparatus is provided comprising receiving circuitry to receive a representation of a circuit comprising a plurality of flops. Categorisation circuitry determines data dependencies between the flops from the representation and generates a categorisation of the flops into one of at least: a vulnerable category, a conditional category, and an isolated category, in dependence on the data dependencies. The categorisation indicates the vulnerability of the flops to transient errors. Output circuitry outputs the categorisation of the flops. The conditional category comprises those of the flops whose change in value is indicated by a change in a value in a corresponding flop in the flops or corresponding signal.

Abstract: A data processing apparatus has at least one circuit block accessible for debugging by a debugger, the block having a set of debug status registers and a debug event register which is set by the circuit block to indicate occurrence of a debug event. Debug interface circuitry interfaces with the set of debug status registers for each circuit block. The circuitry includes at least a first portion which is in a first power domain that remains in a fully powered state while the debugger is connected to the circuitry. Status registers are provided in a second power domain which transitions between the fully powered state and at least one low power state while the debugger is connected to the circuitry. Content of the debug status registers is only accessible to the debugger when the second power domain is in the fully powered state.

Abstract: A data processing apparatus has at least one circuit block accessible for debugging by a debugger, the block having a set of debug status registers and a debug event register which is set by the circuit block to indicate occurrence of a debug event. Debug interface circuitry interfaces with the set of debug status registers for each circuit block. The circuitry includes at least a first portion which is in a first power domain that remains in a fully powered state whilst the debugger is connected to the circuitry. Status registers are provided in a second power domain which transitions between the fully powered state and at least one low power state whilst the debugger is connected to the circuitry. Content of the debug status registers is only accessible to the debugger when the second power domain is in the fully powered state.

Abstract: A virtually indexed and physically tagged memory is described having a cache way size which can exceed the minimum page table size such that aliased virtual addresses VA within the cache way 12 can be mapped to the same physical address PA. Aliasing management logic 10 permits multiple copies of the data from the same physical address to be stored at different virtual indexes within the cache within given or different cache ways.

Abstract: Reset control circuitry is disclosed, for controlling a first reset signal for resetting at least a first portion of a circuit and a further reset signal for resetting at least a second portion of said circuit, said reset control circuitry comprising: an input for receiving an input first reset signal; an input for receiving an input further reset signal; an output for outputting an output first reset signal; and an output for outputting an output further reset signal; said reset control circuitry being responsive to detecting deassertion of said input first reset signal when said input further reset signal is asserted to delay deassertion of said output first reset signal so that said output first reset signal is deasserted at a same time or later than said input further reset signal.

Abstract: A data processing apparatus is disclosed that comprises a pipelined processor, said pipelined processor comprising a processing pipeline for processing instructions in a plurality of stages, at least some of said plurality of stages each comprising storage elements for storing an instruction or decoded instruction being processed in said stage, said storage elements in at least one of said stages comprising settable elements, each of said settable elements being adapted to store a predetermined value in response to a wake up event, said settable elements being arranged such that in response to said wake up event said values stored in said settable elements form an instruction or decoded instruction.

Abstract: The data processing apparatus has processing logic for performing data processing operations and a register bank for storing data associated with the processing logic. The register bank has at least one register group, each register group having a plurality of register sets. The processing logic has an operating state associated with each register group defining how that register group is used, a first operating state being a state in which each register set in the register group is used to support an independent execution thread of the processing logic, and a second operating state being a state in which the register sets of the register group are collectively used to support a single execution thread of the processing logic. Control logic is provided to control how the register sets of each register group are used dependent on the operating state associated with that register group.

Abstract: Interrupt request detection circuitry is disclosed for detecting and outputting interrupt requests to a processor.

Abstract: Interrupt request detection circuitry is disclosed for detecting and outputting interrupt requests to a processor.

Abstract: Reset control circuitry is disclosed, for controlling a first reset signal for resetting at least a first portion of a circuit and a further reset signal for resetting at least a second portion of said circuit, said reset control circuitry comprising: an input for receiving an input first reset signal; an input for receiving an input further reset signal; an output for outputting an output first reset signal; and an output for outputting an output further reset signal; said reset control circuitry being responsive to detecting deassertion of said input first reset signal when said input further reset signal is asserted to delay deassertion of said output first reset signal so that said output first reset signal is deasserted at a same time or later than said input further reset signal.

Abstract: A data processing system is provided having a clock signal comparator comprising a reference input port for receiving a reference clock signal and at least a further input port for receiving respective further clock signal. Checking logic is provided within the clock signal comparator to check for a correspondence between the clock edge of the reference clock signal and a corresponding clock edge of the further clock signal within a predetermined time window. The checking logic is operable to check for the correspondence during operation of the data processing system. The clock-signal comparator can be provided on an integrated circuit or as part of the data processing apparatus having at least two different timing domains such as timing domains associated with two different instances of the same clock.

Abstract: A data processing apparatus is disclosed that comprises a pipelined processor, said pipelined processor comprising a processing pipeline for processing instructions in a plurality of stages, at least some of said plurality of stages each comprising storage elements for storing an instruction or decoded instruction being processed in said stage, said storage elements in at least one of said stages comprising settable elements, each of said settable elements being adapted to store a predetermined value in response to a wake up event, said settable elements being arranged such that in response to said wake up event said values stored in said settable elements form an instruction or decoded instruction.

Abstract: A data processing apparatus and method employing multiple register sets is disclosed. The data processing apparatus has processing logic for performing data processing operations and a register bank for storing data associated with the processing logic. The register bank has at least one register group, each register group having a plurality of register sets. The processing logic has an operating state associated with each register group defining how that register group is used, a first operating state being a state in which each register set in the register group is used to support an independent execution thread of the processing logic, and a second operating state being a state in which the register sets of the register group are collectively used to support a single execution thread of the processing logic. Control logic is provided to control how the register sets of each register group are used dependent on the operating state associated with that register group.