Abstract: One aspect of the present application relates to a storage stable pharmaceutical composition comprising a sulfated glycosaminoglycan having an average molecular weight ranging from 3,000 to 15,000 Daltons, and a pharmaceutical carrier, where the pharmaceutical carrier is mixed with the sulfated glycosaminoglycan, as well as this composition's use in a method of treating a subject for a medically observable improvement. Another aspect of the present application relates to a process for producing a storage stable purified sulfated glycosaminoglycan.

Abstract: A multiple access and data channel scheme is presented for reducing network communication collisions and susceptibility to jamming signals in a distributed network to increase network connectivity and communication throughput. An order wire channel (202) is used to gain access to a data channel (204). To gain access to the data channel (204), a source radio sends a transmit probe (TXP) over the order wire channel (202) to the target radio. The target radio senses its environment and responds with a receive probe (RXP) which comprises data channel transmission parameters including the data channel frequency, transmit power, spread code, and transit timing to be used for the data transmission. Source radio moves to the data channel using the data channel transmission parameters specified by the receive probe (RXP) to communicate with the target radio. If a collision occurs of the order wire channel (202), the source radio retransmits the transmit probe after a random time period.

Abstract: A programmable crypto processing system (10) includes several processing resources (14, 16, 26) implemented on a single ULSI die. The processing system is both key and algorithm agile allowing for simultaneous execution of a variety of cryptographic programs through the use of background staging of the next program and context (key and state) during execution of a current program. The programmable crypto processing system includes a programmable crypto processor (17) for processing data units in accordance with a channel program, a crypto controller (11) for identifying a channel program, two interface processors (13, 15) for asynchronously receiving and transferring data units from and from an external host. Data units identify a particular channel program, and are processed in a selected processing engine in accordance the identified channel program.

Abstract: A programmable cryptographic system (100) provides high performance cryptographic processing support for cryptographic algorithms. Two or more independent cryptographic algorithms may be performed at the same time through the processes of background staging and algorithm multi-tasking. A four stage software instruction pipeline and dynamically programmable function units support high performance cryptographic processing performance on the order of 60 mega bits per second (Mbps) aggregate throughput.

Abstract: A cryptographic controller (100) installs and manages a channel for processing data units. The cryptographic controller (100) performs background staging of programs, context, and data units for the programmable crypto engine (14) and configurable crypto engine (16). The cryptographic controller (100) is a secure, hardware operating system capable of managing high performance crypto processing on the order of 1500 million instructions per second (MIPS).

Abstract: A processing system includes a control flow monitor (CFM) checker for verifying a sequence of instructions performed by a pipelined processor (101). The CFM checker provides fail safe assurance against run-time errors in the sequence of instructions performed by a processor. The CFM checker verifies instruction sequence during run-time within 32 instruction cycles. The processing system provides an improved system and method having a CFM checker which minimizes wasted instruction cycles when performing branch instructions in a software program. Using a prefetch capability of an instruction pipeline and storing fixwords sequentially in memory, eliminates unnecessary instructions to fetch fixword values from external tables, thereby saving instructions and instruction cycles.

Abstract: A configurable cryptographic processing engine (100) provides high performance cryptographic processing support for symmetric combiner type cryptographic algorithms. As many as two independent cryptographic algorithms may be performed at the same time through the processes of background staging and algorithm multi-tasking. A 3-stage instruction pipeline, dynamically configurable cryptographic co-processor (550), and 32-bit RISC based architecture support high performance cryptographic processing performance on the order of 60 Mbps aggregate throughput.

Abstract: Interface processor (IP)(50) sends and receives data units to and from an external host and a processor. The IP is capable of simultaneous, full duplex operation via high speed serial and parallel interfaces. The IP provides a highly flexible and configurable interface which is capable of interfacing to a variety of systems with minimal external hardware. The IP also provides a method of converting received data into data packets. The IP provides buffering of multiple data packets for use in systems having "bursty" data traffic. The IP has a memory expansion capability allowing for changeable buffer capacities.