Abstract: The present invention relates to systems and methods for ingesting of raw client data into a supply chain optimization system. The client enterprise data system (EDS) provides raw data, typically in tabular format across many files, to a data management module of the optimization system. This data is then profiled. and a set of mapping AI models is applied to the profiled data. Each of the plurality of mapping AI models corresponds to a single input feature of the optimization model. As the mapping models are applied, a live preview is generated. This live preview is reviewable by a human operator, and human input can be provided. When there is input, the individual mapping model is updated (without impacting the other mapping models), and a new live preview for that given feature is generated. The resulting standardized feature set may be consumed by the supply chain optimization model.

Abstract: This application relates to a building energy analysis and management system for measurement and verification of building performance. The system can analyze, optimize, manage, maintain, trouble shoot, and/or modify building systems, such as HVAC systems, in connection with the building energy usage. Measurements may be gathered for one or more HVAC units coupled to pressure independent valves, and sent to one or more Surge Panels that pass data to remote analysis servers, which can receive other system or external data. The analysis servers compare measurements to predicted values and can standardize the predicted values to account for external conditions. The comparison can result in difference values used to generate probable causes and optimization recommendations. The system outputs reports or other data display using a graphical user interface that can be adjusted for an anticipated user.

Abstract: An electrostatic discharge protection circuit capable of clamping both positive and negative ESD events and passing signals is provided. Generally, the circuit includes a p-channel field-effect transistor (PFET) clamp coupled to a pin to be protected, the PFET clamp including a plurality of PFETs in a DN-well, an n-channel field-effect transistors (NFET) clamp coupled between ground and the pin through the PFET clamp, the NFET clamp including a plurality of NFETs coupled in series, and a bias network for biasing a voltage of the DN well to substantially equal a voltage on the pin when the voltage on the pin is greater than ground potential, and to ground potential when the pin voltage is less than ground potential. The plurality of are PFETs coupled in parallel between the pin and the NFET clamp, each of the PFETs is coupled to the pin though one of a plurality ballast resistors.

Abstract: An electrostatic discharge protection circuit capable of clamping both positive and negative ESD events and passing signals is provided. Generally, the circuit includes a p-channel field-effect transistor (PFET) clamp coupled to a pin to be protected, the PFET clamp including a plurality of PFETs in a DN-well, an n-channel field-effect transistors (NFET) clamp coupled between ground and the pin through the PFET clamp, the NFET clamp including a plurality of NFETs coupled in series, and a bias network for biasing a voltage of the DN well to substantially equal a voltage on the pin when the voltage on the pin is greater than ground potential, and to ground potential when the pin voltage is less than ground potential. The plurality of are PFETs coupled in parallel between the pin and the NFET clamp, each of the PFETs is coupled to the pin though one of a plurality ballast resistors.

Abstract: A system and method for combining positive and negative voltage electrostatic discharge (ESD) protection into a clamp that uses cascoded circuitry, including detecting, by an electrostatic discharge protection system, a voltage pulse on an input pin of an integrated circuit (IC) controller, the IC controller coupled between a power supply node and a ground supply node; determining, by the ESD protection circuit, an ESD event on the input pin based on the voltage detected on the input pin; and/or controlling, by the ESD protection circuit during the ESD event, one or more clamps to transport the voltage pulse from the input pin of the IC controller to the power supply node.

Abstract: An electrostatic discharge protection circuit capable of clamping both positive and negative ESD events and passing signals is provided. Generally, the circuit includes a p-channel field-effect transistor (PFET) clamp coupled to a pin to be protected, the PFET clamp including a plurality of PFETs in a DN-well, an n-channel field-effect transistors (NFET) clamp coupled between ground and the pin through the PFET clamp, the NFET clamp including a plurality of NFETs coupled in series, and a bias network for biasing a voltage of the DN well to substantially equal a voltage on the pin when the voltage on the pin is greater than ground potential, and to ground potential when the pin voltage is less than ground potential. The plurality of are PFETs coupled in parallel between the pin and the NFET clamp, each of the PFETs is coupled to the pin though one of a plurality ballast resistors.

Abstract: A system and method for combining positive and negative voltage electrostatic discharge (ESD) protection into a clamp that uses cascoded circuitry, including detecting, by an electrostatic discharge protection system, a voltage pulse on an input pin of an integrated circuit (IC) controller, the IC controller coupled between a power supply node and a ground supply node; determining, by the ESD protection circuit, an ESD event on the input pin based on the voltage detected on the input pin; and/or controlling, by the ESD protection circuit during the ESD event, one or more clamps to transport the voltage pulse from the input pin of the IC controller to the power supply node.

Abstract: The present disclosure is directed to biomimetic membranes and methods of manufacturing such membranes that include structural features that mimic the structures of cellular membrane channels and produce membrane designs capable of high selectivity and high permeability or absorptivity. The membrane structure, material and chemistry can be selected to perform liquid separations, gas separation and capture, ion transport and adsorption for a variety of applications.

Abstract: The present disclosure is directed to biomimetic membranes and methods of manufacturing such membranes that include structural features that mimic the structures of cellular membrane channels and produce membrane designs capable of high selectivity and high permeability or adsorptivity. The membrane structure, material and chemistry can be selected to perform liquid separations, gas separation and capture, ion transport and adsorption for a variety of applications.

Abstract: A characterization method for a device under test includes applying a bias voltage to a test circuit. The test circuit includes a first transistor coupled to the device under test, a second transistor coupled to the device under test and to the first transistor. A third transistor is coupled to a dummy device, a fourth transistor is coupled to the dummy device and to the third transistor. The transistors are of a common type. The characterization method further includes applying non-overlapping clocking signals to transistors of the test circuit to produce test signals for application to the device under test and detecting a current in one or more transistors from the device under test. The bias voltage is further varied to characterize the device under test.

Abstract: A multiplexed transistor characterization and modeling structure for testing a plurality of transistors, The characterization and modeling structure comprises a common substrate pad, a common source pad, a plurality of drain pads, and a plurality of gate pads. The characterization and modeling structure further comprises a plurality of individual transistors. Each individual transistor comprises a substrate connected to the common substrate pad, a source connected to the common source pad, a drain connected to a single drain pad, and a gate connected to a single gate pad, wherein each individual transistor is connected to a different drain pad and gate pad combination.

Abstract: Disclosed herein is a method for forming an interconnect line having low conductor line capacitance between devices formed on an integrated circuit.