Abstract: A method of automatically queuing calls for later transmission in connection-oriented networks instead of blocking them when network resources are unavailable at the time the request is received, as currently done. A simple call queuing method holds up call setup messages at each switch along an end-to-end path of a network until resources become available. This simple, known queuing method suffers from poor network utilization and long call queuing delays. However, if calls that can be queued have known holding times, a call scheduling method that results in reduced call queuing delays and improved network utilization according to the present invention can be realized.

Abstract: An address interworking system and method for an internetwork that includes a first network using first network addressing communicating via one or more internetworking gateways with a second network using second network addressing. The gateways register one or more first network addresses in the second network as first network address-encapsulated or- mapped second network addresses. Reachability information regarding the first network-encapsulated or -mapped second network addresses is then disseminated through the second network. When a communication request containing a first network destination address is received from the first network at one of the gateways, the receiving gateway performs encapsulation or mapping of the first network destination address into a first network-encapsulated or -mapped second network destination address.

Abstract: A telecommunication network having a telephonic switch with a message signal controller connected to a plurality of other telephonic switches by a plurality of associated common-channel signaling links, each associated common-channel signaling link terminating at the message signaling interface at the telephonic switch and one of the plurality of other telephonic switches for transmission of telephonic signaling information.

Abstract: A method of automatically queuing calls for later transmission in connection-oriented networks instead of blocking them when network resources are unavailable at the time the request is received, as currently done. A simple call queuing method holds up call setup messages at each switch along an end-to-end path of a network until resources become available. This simple, known queuing method suffers from poor network utilization and long call queuing delays. However, if calls that can be queued have known holding times, a call scheduling method that results in reduced call queuing delays and improved network utilization according to the present invention can be realized.

Abstract: The transmission of messages among multiple processors is controlled by the use of token and message interrupts. A token interrupt must be received from the processor sought to perform message processing. Failure to receive such a token interrupt prohibits requesting processors from making processing demands, i.e. sending a message interrupt, to the processor. Message interrupts, which may only be transmitted following receipt of a token interrupt, identify commands and user messages to be processed by a receiving processor. This permits instructions and multiple messages to be handled by a processor based on receipt of a single message interrupt. This technique also allows a processor under a temporary heavy load to defer the handling of other processing requests by delaying the transmission of a token interrupt.

Abstract: Disclosed is a combinational logic arrangement for use in a data processor that selectively performs a plurality of bit manipulations or logic operations including shift, rotate, and insert under mask. The arrangement is controlled by a single instruction format which specifies the parameters needed for each of the operations. The logic arrangement interprets a data word as a bit string with two boundary lines that divide the string into three regions: left region, quantum region and right region. The logic circuit operates upon the left and/or right regions of an output word to either clear all bits, set all bits, propagate the sign bit of an input word or retain the information in the left and right regions of an input data word. The circuit then inserts a quantum of bits obtained from a specified region of another input data word into the output data word starting at any desired location.